PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 59

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.5
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the Pro-
gram Counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 5-4.
FIGURE 5-4:
EXAMPLE 5-2:
 2003 Microchip Technology Inc.
1. MOVLW 55h
2. MOVWF PORTB
3. BRA
4. BSF
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
OSC2/CLKO
Clocking Scheme/Instruction
Cycle
(RC mode)
SUB_1
PORTA, BIT3 (Forced NOP)
OSC1
Q4
PC
Q2
Q3
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-2)
Fetch INST (PC)
Q2
Fetch 1
T
PC
CY
0
Q3
Q4
Execute 1
Fetch 2
PIC18F2220/2320/4220/4320
T
CY
1
Q1
Execute INST (PC)
Fetch INST (PC+2)
Execute 2
Q2
Fetch 3
T
PC+2
CY
2
5.6
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 5-2).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Q4
Execute 3
Fetch 4
Instruction Flow/Pipelining
T
CY
3
Q1
Execute INST (PC+2)
Fetch INST (PC+4)
Fetch SUB_1 Execute SUB_1
Flush (NOP)
Q2
T
PC+4
CY
4
Q3
Q4
DS39599C-page 57
T
CY
Internal
Phase
Clock
5