PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 135

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.0
The standard CCP (Capture/Compare/PWM) module
contains a 16-bit register that can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register. Table 15-1 shows
the timer resources required for each of the CCP
module modes.
The operation of CCP1 is identical to that of CCP2, with
the exception of the special event trigger. Therefore,
operation of a CCP module is described with respect to
CCP1 except where noted. Table 15-2 shows the
interaction of the CCP modules.
REGISTER 15-1:
 2003 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULES
bit 7-6
bit 5-4
bit 3-0
CCPxCON: CCP MODULE CONTROL REGISTER
bit 7
Reserved: Read as ‘0’.
See Section 16.0 “Enhanced Capture/Compare/PWM (ECCP) Module”.
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP pin Low; on compare match, force CCP pin High
1001 = Compare mode, initialize CCP pin High; on compare match, force CCP pin Low
1010 = Compare mode, generate software interrupt on compare match (CCPxIF bit is set, CCP
1011 = Compare mode, trigger special event (CCP2IF bit is set)
11xx = PWM mode
Legend:
R = Readable bit
- n = Value at POR
U-0
—
(CCPxIF bit is set)
(CCPxIF bit is set)
pin operates as a port pin for input and output)
U-0
—
PIC18F2220/2320/4220/4320
DCxB1
R/W-0
W = Writable bit
‘1’ = Bit is set
DCxB0
R/W-0
Note:
CCPxM3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
In 28-pin devices, both CCP1 and CCP2
function as standard CCP modules. In
40-pin devices, CCP1 is implemented as
an Enhanced CCP module, offering addi-
tional capabilities in PWM mode. Capture
and Compare modes are identical in all
modules regardless of the device.
Please see Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Mod-
ule” for a discussion of the enhanced
PWM capabilities of the CCP1 module.
CCPxM2
R/W-0
x = Bit is unknown
CCPxM1
R/W-0
DS39599C-page 133
CCPxM0
R/W-0
bit 0