PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 115

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 10-9:
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
 2003 Microchip Technology Inc.
PORTE
LATE
TRISE
ADCON1
Legend:
Note 1:
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
MCLR/V
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1:
Name
Name
PP
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used by PORTE.
Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0).
Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
/RE3
Bit 7
IBF
—
—
—
PORTE FUNCTIONS
Bit#
bit 0
bit 1
bit 2
bit 3
Bit 6
OBF
—
—
—
Buffer Type
VCFG1
ST/TTL
ST/TTL
ST/TTL
IBOV
Bit 5
—
—
ST
(1)
(1)
(1)
PSPMODE
VCFG0
Bit 4
—
—
PIC18F2220/2320/4220/4320
Input/output port pin, analog input or read control input in Parallel Slave
Port mode.
For RD (PSP Control mode):
1 = PSP is Idle
0 = Read operation. Reads PORTD register (if chip selected).
Input/output port pin, analog input or write control input in Parallel
Slave Port mode.
For WR (PSP Control mode):
1 = PSP is Idle
0 = Write operation. Writes PORTD register (if chip selected).
Input/output port pin, analog input or chip select control input in Parallel
Slave Port mode.
For CS (PSP Control mode):
1 = PSP is Idle
0 = External device is selected
Input only port pin or programming voltage input (if MCLR is disabled);
Master Clear input or programming voltage input (if MCLR is enabled).
PCFG3
RE3
Bit 3
—
—
(1)
LATE Data Latch Register
PORTE Data Direction bits
PCFG2
Bit 2
RE2
PCFG1
Bit 1
RE1
Function
PCFG0
Bit 0
RE0
---- q000
---- -xxx
0000 -111
--00 0000
POR, BOR
Value on
DS39599C-page 113
---- q000
---- -uuu
0000 -111
--00 0000
Value on
all other
Resets