PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 288

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
MOVSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (dest.)
Description
Words:
Cycles:
Example:
DS39682B-page 286
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
FSR2
Contents
of 85h
Contents
of 86h
FSR2
Contents
of 85h
Contents
of 86h
Q1
source addr
Determine
Determine
dest addr
Move Indexed to Indexed
MOVSS [z
0 ≤ z
0 ≤ z
((FSR2) + z
None
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘z
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a
2
2
MOVSS [05h], [06h]
1110
1111
Q2
=
=
=
=
=
=
s
d
≤ 127
≤ 127
80h
33h
11h
80h
33h
33h
s
s
1011
xxxx
) → ((FSR2) + z
source addr
], [z
Determine
Determine
dest addr
d
Q3
]
s
’ or ‘z
1zzz
xzzz
d
’,
source reg
to dest reg
NOP
d
)
Read
Write
Q4
zzzz
zzzz
.
Preliminary
s
d
PUSHL
Syntax:
Operands:
Operation:
Status Affected: None
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FSR2H:FSR2L
Memory (01ECh)
FSR2H:FSR2L
Memory (01ECh)
Q1
Store Literal at FSR2, Decrement FSR2
PUSHL k
0 ≤ k ≤ 255
k → (FSR2),
FSR2 – 1 → FSR2
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
is decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
1
1
1111
PUSHL 08h
Read ‘k’
Q2
© 2006 Microchip Technology Inc.
1010
=
=
=
=
Process
data
Q3
01ECh
00h
01EBh
08h
kkkk
destination
Write to
Q4
kkkk