PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 177

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.4.9
A Repeated Start condition occurs when the RSEN bit
(SSPxCON2<1>) is programmed high and the I
module is in the Idle state. When the RSEN bit is set,
the SCLx pin is asserted low. When the SCLx pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPxADD<6:0> and begins counting.
The SDAx pin is released (brought high) for one Baud
Rate Generator count (T
Generator times out, if SDAx is sampled high, the SCLx
pin will be deasserted (brought high). When SCLx is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and begins count-
ing. SDAx and SCLx must be sampled high for one
T
SDAx pin (SDAx = 0) for one T
Following this, the RSEN bit (SSPxCON2<1>) will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDAx pin held low. As
soon as a Start condition is detected on the SDAx and
SCLx pins, the S bit (SSPxSTAT<3>) will be set. The
SSPxIF bit will not be set until the Baud Rate Generator
has timed out.
FIGURE 15-20:
© 2006 Microchip Technology Inc.
BRG
. This action is then followed by assertion of the
Write to SSPxCON2
I
START CONDITION TIMING
2
C MASTER MODE REPEATED
on falling edge of ninth clock,
RSEN bit set by hardware
REPEATED START CONDITION WAVEFORM
BRG
SDAx
SCLx
occurs here:
). When the Baud Rate
BRG
end of Xmit
while SCLx is high.
SDAx = 1,
SCLx (no change)
2
C logic
Preliminary
T
SDAx = 1,
SCLx = 1
BRG
PIC18F45J10 FAMILY
Immediately following the SSPxIF bit getting set, the
user may write the SSPxBUF with the 7-bit address in
7-bit mode or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
15.4.9.1
If the user writes the SSPxBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
T
Note:
BRG
Note 1: If RSEN is programmed while any other
Sr = Repeated Start
2: A bus collision during the Repeated Start
T
BRG
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPxCON2 is disabled until the Repeated
Start condition is complete.
event is in progress, it will not take effect.
condition occurs if:
• SDAx is sampled low when SCLx
• SCLx goes low before SDAx is
WCOL Status Flag
At completion of Start bit,
hardware clears RSEN bit
goes from low-to-high.
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
S bit set by hardware
and sets SSPxIF
Write to SSPxBUF occurs here
T
BRG
1st bit
T
BRG
DS39682B-page 175