PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 241

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 20-5:
20.5.3
By entering a power-managed mode, the clock
multiplexor selects the clock source selected by the
OSCCON register. Fail-Safe Monitoring of the
power-managed
power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexor. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTOSC
source.
© 2006 Microchip Technology Inc.
Note:
Sample Clock
CM Output
FSCM INTERRUPTS IN
POWER-MANAGED MODES
OSCFIF
Device
Output
Clock
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
clock
FSCM TIMING DIAGRAM
source
resumes
CM Test
in
Preliminary
the
PIC18F45J10 FAMILY
20.5.4
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is either EC or INTRC modes, monitoring
can begin immediately following these events.
For HS mode, the situation is somewhat different.
Since the oscillator may require a start-up time consid-
erably longer than the FSCM sample clock time, a false
clock failure may be detected. To prevent this, the
internal oscillator block is automatically configured as
the device clock and functions until the primary clock is
stable (the OST timer has timed out). This is identical
to Two-Speed Start-up mode. Once the primary clock is
stable, the INTRC returns to its role as the FSCM
source.
As noted in Section 20.4.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
Note:
CM Test
Oscillator
Failure
POR OR WAKE-UP FROM SLEEP
The same logic that prevents false oscilla-
tor failure interrupts on POR, or wake from
Sleep, will also prevent the detection of
the oscillator’s failure to start at all
following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
Detected
Failure
CM Test
DS39682B-page 239