PIC18F25K22-I/SO Microchip Technology Inc., PIC18F25K22-I/SO Datasheet - Page 411
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PIC18F25K22-I/SO
Manufacturer Part Number
PIC18F25K22-I/SO
Description
32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP, 28 SOIC .300in TUBE
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F25K22-I/SO
A/d Inputs
17-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Price
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Part Number:
PIC18F25K22-I/SO
Manufacturer:
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Quantity:
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CALLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description
Words:
Cycles:
Example:
2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PCLATH =
PCLATU =
W
PC
TOS
PCLATH =
PCLATU =
W
Q1
No
=
=
=
=
=
operation
Subroutine Call Using WREG
CALLW
None
(PC + 2) TOS,
(W) PCL,
(PCLATH) PCH,
(PCLATU) PCU
None
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a
new next instruction is fetched.
Unlike
update W, Status or BSR.
1
2
HERE
WREG
Read
0000
Q2
No
address (HERE)
10h
00h
06h
001006h
address (HERE + 2)
10h
00h
06h
CALL
CALLW
0000
PUSH PC to
, there is no option to
operation
NOP
stack
Q3
No
instruction while the
0001
operation
operation
Q4
No
No
0100
Preliminary
MOVSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
PIC18(L)F2X/4XK22
Before Instruction
After Instruction
Decode
Decode
FSR2
Contents
of 85h
REG2
FSR2
Contents
of 85h
REG2
Q1
source addr
No dummy
Determine
operation
Move Indexed to f
MOVSF [z
0 z
0 f
((FSR2) + z
None
The contents of the source register are
moved to destination register ‘f
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z
FSR2. The address of the destination
register is specified by the 12-bit literal
‘f
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
2
2
MOVSF
d
’ in the second word. Both addresses
read
1110
1111
Q2
No
=
=
=
=
=
=
d
s
4095
127
s
’ in the first word to the value of
80h
33h
11h
80h
33h
33h
[05h], REG2
s
s
1011
ffff
], f
) f
source addr
Determine
operation
d
Q3
No
d
DS41412D-page 411
0zzz
ffff
source reg
register ‘f’
(dest)
Read
Write
d
Q4
ffff
zzzz
’. The
s
d
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