PIC18F25K22-I/SO Microchip Technology Inc., PIC18F25K22-I/SO Datasheet - Page 390
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F25K22-I/SO
Manufacturer Part Number
PIC18F25K22-I/SO
Description
32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP, 28 SOIC .300in TUBE
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F25K22-I/SO
A/d Inputs
17-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K22-I/SO
Manufacturer:
MICROCHIP
Quantity:
3 000
Company:
Part Number:
PIC18F25K22-I/SO
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
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PIC18(L)F2X/4XK22
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS41412D-page 390
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
Inclusive OR literal with W
IORLW k
0 k 255
(W) .OR. k W
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
1
1
IORLW
literal ‘k’
Read
0000
Q2
9Ah
BFh
1001
35h
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
Preliminary
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
RESULT =
W
RESULT =
W
Q1
=
=
register ‘f’
Inclusive OR W with f
IORWF
0 f 255
d [0,1]
a [0,1]
(W) .OR. (f) dest
N, Z
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
IORWF
Read
0001
Q2
13h
91h
13h
93h
2010 Microchip Technology Inc.
RESULT, 0, 1
f {,d {,a}}
00da
Process
Data
Q3
ffff
for details.
destination
Write to
Q4
ffff
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