PIC18F25K22-I/SO Microchip Technology Inc., PIC18F25K22-I/SO Datasheet - Page 354
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PIC18F25K22-I/SO
Manufacturer Part Number
PIC18F25K22-I/SO
Description
32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP, 28 SOIC .300in TUBE
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F25K22-I/SO
A/d Inputs
17-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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PIC18(L)F2X/4XK22
REGISTER 24-4:
DS41412D-page 354
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
MCLRE
R/P-1
2:
PIC18(L)F2XK22 devices only.
PIC18(L)F4XK22 devices only.
MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled; RE3 input pin disabled
0 = RE3 input pin enabled; MCLR disabled
Unimplemented: Read as ‘0’
P2BMX: P2B Input MUX bit
1 = P2B is on RB5
0 = P2B is on RC0
T3CMX: Timer3 Clock Input MUX bit
1 = T3CKI is on RC0
0 = T3CKI is on RB5
HFOFST: HFINTOSC Fast Start-up bit
1 = HFINTOSC starts clocking the CPU without waiting for the oscillator to stabilize
0 = The system clock is held off until the HFINTOSC is stable
CCP3MX: CCP3 MUX bit
1 = CCP3 input/output is multiplexed with RB5
0 = CCP3 input/output is multiplexed with RC6
PBADEN: PORTB A/D Enable bit
1 = ANSELB<5:0> resets to 1, PORTB<5:0> pins are configured as analog inputs on Reset
0 = ANSELB<5:0> resets to 0, PORTB<4:0> pins are configured as digital I/O on Reset
CCP2MX: CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
CCP3 input/output is multiplexed with RE0
P2B is on RD2
U-0
—
CONFIG3H: CONFIGURATION REGISTER 3 HIGH
P = Programmable bit
P2BMX
R/P-1
(1)
(2)
T3CMX
R/P-1
Preliminary
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
HFOFST
(2)
(1)
R/P-1
CCP3MX
R/P-1
2010 Microchip Technology Inc.
PBADEN
R/P-1
CCP2MX
R/P-1
bit 0
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