PIC18F25K22-I/SO Microchip Technology Inc., PIC18F25K22-I/SO Datasheet - Page 188
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PIC18F25K22-I/SO
Manufacturer Part Number
PIC18F25K22-I/SO
Description
32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP, 28 SOIC .300in TUBE
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F25K22-I/SO
A/d Inputs
17-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18(L)F2X/4XK22
14.4
The enhanced PWM function described in this section is
available for CCP modules ECCP1, ECCP2 and
ECCP3, with any differences between modules noted.
The enhanced PWM mode generates a Pulse-Width
Modulation (PWM) signal on up to four different output
pins with up to 10 bits of resolution. The period, duty
cycle, and resolution are controlled by the following
registers:
• PRx registers
• TxCON registers
• CCPRxL registers
• CCPxCON registers
The ECCP modules have the following additional PWM
registers which control Auto-shutdown, Auto-restart,
Dead-band Delay and PWM Steering modes:
• ECCPxAS registers
• PSTRxCON registers
• PWMxCON registers
The enhanced PWM module can generate the following
five PWM Output modes:
• Single PWM
• Half-Bridge PWM
• Full-Bridge PWM, Forward Mode
• Full-Bridge PWM, Reverse Mode
• Single PWM with PWM Steering Mode
FIGURE 14-5:
DS41412D-page 188
Note 1:
CCPRxH (Slave)
Duty Cycle Registers
Comparator
PWM (Enhanced Mode)
CCPRxL
PRx
TMRx
2:
Comparator
The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time
base.
PxC and PxD are not available on Half-Bridge ECCP Modules.
(1)
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
Clear Timer,
toggle PWM pin and
latch duty cycle
DCxB<1:0>
R
S
PxM<1:0>
Q
Preliminary
PWMxCON
Controller
Output
2
CCPx/PxA
PxB
PxC
PxD
To select an Enhanced PWM Output mode, the
PxM<1:0> bits of the CCPxCON register must be
configured appropriately.
The PWM outputs are multiplexed with I/O pins and are
designated PxA, PxB, PxC and PxD. The polarity of the
PWM pins is configurable and is selected by setting the
CCPxM bits in the CCPxCON register appropriately.
Figure 14-5
diagram of the Enhanced PWM module.
Table 14-12
Enhanced PWM modes.
4
CCPxM<3:0>
Note 1: The corresponding TRIS bit must be
2: Clearing the CCPxCON register will
3: Any pin not used in the enhanced PWM
4: To
TRISx
TRISx
TRISx
TRISx
cleared to enable the PWM output on the
CCPx pin.
relinquish control of the CCPx pin.
mode is available for alternate pin
functions, if applicable.
incomplete waveform when the PWM is
first enabled, the ECCP module waits
until the start of a new PWM period
before generating a PWM signal.
shows an example of a simplified block
shows the pin assignments for various
prevent
2010 Microchip Technology Inc.
the
CCPx/PxA
PxB
PxD
PxC
generation
(2)
(2)
of
an
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