PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet - Page 88

• Manufacturer Part Number: PIC12F683-E/P
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-E/P

• A/d Inputs: 4 Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F683
12.4.2
An overflow (FFh
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled
(INTCON<5>) bit. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
FIGURE 12-7:
DS41211B-page 86
TMR0 INTERRUPT
IOC-GP0
IOC-GP1
IOC-GP2
IOC-GP3
IOC-GP4
IOC-GP5
TMR2IF
TMR2IE
TMR1IE
TMR1IF
CCP1IF
CCP1IE
OSFIF
OSFIE
CMIF
CMIE
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
ADIF
ADIE
EEIE
EEIF
00h) in the TMR0 register will set
by
INTERRUPT LOGIC
setting/clearing
T0IE
Preliminary
GPIE
INTF
INTE
GPIF
PEIE
T0IF
T0IE
GIE
12.4.3
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOC register.
Note:
GPIO INTERRUPT
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF
interrupt flag may not get set.
Wake-up (If in Sleep mode)
 2004 Microchip Technology Inc.
Interrupt to CPU