PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet - Page 102
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC12F683-E/P
Manufacturer Part Number
PIC12F683-E/P
Description
8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O, PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC12F683-EP.pdf
(148 pages)
Specifications of PIC12F683-E/P
A/d Inputs
4 Channel, 10-Bit
Comparators
1
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Frequency
20 MHz
Input Output
6
Memory Type
Flash
Number Of Bits
8
Package Type
8-pin PDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Serial Interface
None
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC12F683
MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
MOVWF
Syntax:
Operands:
Operation:
Status Affected: None
Encoding:
Description:
Words:
Cycles:
Example:
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS41211B-page 100
Move W to f
[ label ]
0
(W)
Move data from W register to register ‘f’.
1
1
Before Instruction
After Instruction
MOVWF
Move Literal to W
[ label ]
0
k
None
The eight-bit literal ‘k’ is loaded into
the W register. The don’t cares will
assemble as ‘0’s
1
1
After Instruction
No Operation
[ label ]
None
No operation
None
No operation.
1
1
MOVLW
f
00
NOP
11
00
k
127
(f)
(W)
OPTION =
W
OPTION =
W
MOVWF
255
OPTION
W
0000
MOVLW k
0x5A
NOP
00xx
0000
=
=
=
.
0x5A
f
1fff
kkkk
0xFF
0x4F
0x4F
0x4F
0xx0
ffff
kkkk
0000
Preliminary
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
RETFIE
Syntax:
Operands:
Operation:
Status Affected: None
Encoding:
Description:
Words:
Cycles:
Example:
Return from Interrupt
[ label ]
None
TOS
Return from interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in the
PC. Interrupts are enabled by setting
Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
1
2
After Interrupt
RETFIE
Inclusive OR W with f
[ label ]
0
d
(W) .OR. (f)
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Inclusive OR Literal with W
[ label ]
0
(W) .OR. k
Z
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
00
f
[0,1]
k
PC, 1
2004 Microchip Technology Inc.
PC =
GIE =
127
RETFIE
255
0000
IORWF
IORLW k
GIE
(W)
TOS
1
(destination)
0000
f,d
1001
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