PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet - Page 42

• Manufacturer Part Number: PIC12F683-E/P
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-E/P

• A/d Inputs: 4 Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F683
5.3
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 T
a small RC delay of 20 ns) and low for at least 2 T
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.4
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this data sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS<2:0> bits (OPTION_REG<2:0>).
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
TABLE 5-1:
DS41211B-page 40
01h
0Bh/8Bh INTCON
81h
85h
Legend:
Addr
Note:
Using Timer0 with an External
Clock
Prescaler
TMR0
OPTION_REG GPPU
TRISIO
— = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
The ANSEL (9Fh) and CMCON0 (19h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
Name
REGISTERS ASSOCIATED WITH TIMER0
Timer0 Module Register
Bit 7
GIE
—
INTEDG
PEIE
Bit 6
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
T0CS
Bit 5
T0IE
MOVWF 1,
OSC
(and
OSC
Preliminary
T0SE
INTE
Bit 4
GPIE
Bit 3
PSA
execution). To avoid an unintended device Reset, the
5.4.1
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program
following instruction sequence (Example 5-1 and
Example 5-2) must be executed when changing the
prescaler assignment from Timer0 to WDT.
EXAMPLE 5-1:
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 5-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 5-2:
BCF
CLRWDT
CLRF
BSF
MOVLW
MOVWF
CLRWDT
MOVLW
MOVWF
BCF
CLRWDT
BSF
MOVLW
MOVWF
BCF
Bit 2
T0IF
PS2
STATUS,RP0
TMR0
STATUS,RP0
b’00101111’
OPTION_REG
b’00101xxx’
OPTION_REG
STATUS,RP0
STATUS,RP0
b’xxxx0xxx’
OPTION_REG
STATUS,RP0
SWITCHING PRESCALER
ASSIGNMENT
INTF
Bit 1
PS1
CHANGING PRESCALER
(TIMER0
CHANGING PRESCALER
(WDT
GPIF
Bit 0
PS0
 2004 Microchip Technology Inc.
;Bank 0
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
;Required if desired
; PS2:PS0 is
; 000 or 001
;
;Set postscaler to
; desired WDT rate
;Bank 0
;Clear WDT and
; prescaler
;Bank 1
;Select TMR0,
; prescale, and
; clock source
;
;Bank 0
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
POR, BOD
Value on
TIMER0)
WDT)
Value on
all other
Resets