PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet - Page 83

• Manufacturer Part Number: PIC12F683-E/P
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-E/P

• A/d Inputs: 4 Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.3.5
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator configu-
ration and PWRTE bit status. For example, in EC mode
with PWRTE bit erased (PWRT disabled), there will be
no time-out at all. Figure 12-4, Figure 12-5 and
Figure 12-6 depict time-out sequences. The device can
execute code from the INTOSC while OST is active by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 3.6 “Two-Speed Clock Start-up Mode” and
Section 3.7 “Fail-Safe Clock Monitor”).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to synchronize more than one PIC12F683 device
operating in parallel.
Table 12-5 shows the Reset conditions for some
special registers, while Table 12-4 shows the Reset
conditions for all the registers.
TABLE 12-1:
TABLE 12-2:
TABLE 12-3:
 2004 Microchip Technology Inc.
03h
8Eh
Legend:
Note 1:
XT, HS, LP
RC, EC, INTOSC
Address
Legend: u = unchanged, x = unknown
Configuration
POR
Oscillator
0
1
u
u
u
u
STATUS
PCON
u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition.
Shaded cells are not used by BOD.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
TIME-OUT SEQUENCE
Name
BOD
u
0
u
u
u
u
TIME-OUT IN VARIOUS SITUATIONS
PCON BITS AND THEIR SIGNIFICANCE
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
T
PWRT
Bit 7
IRP
—
PWRTE = 0
TO
1
1
0
0
u
1
+ 1024 • T
T
PWRT
Bit 6
RP1
—
Power-up
PD
ULPWUE SBODEN
OSC
1
1
u
0
u
0
Bit 5
RPO
PWRTE = 1
1024 • T
Power-on Reset
Brown-out Detect
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
Bit 4
TO
—
Preliminary
OSC
Bit 3
PD
—
T
PWRT
12.3.6
The Power Control register PCON (address 8Eh) has
two status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent Resets to see if BOD = 0, indicating that
a Brown-out has occurred. The BOD status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (BODEN<1:0> = 00 in the
Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
gone too low).
For more information, see Section 4.2.3 “Ultra Low-
Power Wake-up” and Section 12.3.4 “Brown-out
Detect (BOD)”.
PWRTE = 0
Bit 2
—
+ 1024 • T
T
Z
PWRT
Brown-out Detect
POWER CONTROL (PCON)
REGISTER
Condition
Bit 1
POR
DC
OSC
BOD
Bit 0
C
PWRTE = 1
1024 • T
PIC12F683
—
0001 1xxx
--01 --qq
POR, BOD
Value on
OSC
DS41211B-page 81
Wake-up from
1024 • T
DD
000q quuu
--0u --uu
Sleep
Resets
Value on
all other
may have
—
OSC
(1)