DSPIC30F2020-30I/SP Microchip Technology Inc., DSPIC30F2020-30I/SP Datasheet - Page 186

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DSPIC30F2020-30I/SP

Manufacturer Part Number
DSPIC30F2020-30I/SP
Description
DSP, 16-Bit, 12KB Flash, 512 RAM, 21 I/O, SDIP-28
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet

Specifications of DSPIC30F2020-30I/SP

A/d Inputs
8-Channels, 10-Bit
Comparators
4
Cpu Speed
30 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Ios
21
Memory Type
Flash
Number Of Bits
16
Package Type
28-pin SPDIP
Programmable Memory
12K Bytes
Ram Size
512 Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
3-5.5
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device
dsPIC30F1010/202X
Example 16-1 shows a code sequence for using the
ADBASE register to implement ADC Input Pair Inter-
rupt Handling. When the ADBASE register is read, it
contains the sum of the base address of the jump table
and the encoded ADC channel pair number left shifted
by 2 bits.
EXAMPLE 16-1:
DS70178C-page 184
; Initialize and enable the ADC interrupt
; Code to Initialize the rest of the ADC registers
; ADC Interrupt Handler
__ADCInterrupt:
; Here's the Jump Table
; Note: It is important to clear the individual IRQ flags in the ADC AFTER the IRQ flags
in the interrupt controller. Failure to do so may cause interrupt requests to be lost
JMP_TBL:
MOV
MOV WO, ADBASE
BSET
BSET
BSET
BCLR
BCLR
BSET
...
...
...
PUSH.S
BCLR
MOV
GOTO
BCLR
BRA
BCLR
BRA
BCLR
BRA
BCLR
BRA
BCLR
BRA
#handle(JMP_TBL),W0
IPC2,#12
IPC2,#13
IPC2,#14
IFS0,#11
ADSTAT
IEC0,#11
IFSO,#11
ADBASE, W0
W0
ADSTAT,#0
ADC_PAIR0_PROC
ADSTAT,#1
ADC_PAIR1_PROC
ADSTAT,#2
ADC_PAIR2_PROC
ADSTAT,#3
ADC_PAIR3_PROC
ADSTAT,#4
ADC_PAIR4_PROC
ADC BASE REGISTER CODE
; Load the base address of the ISR Jump
; table in ADBASE.
; Set up the interrupt priority
; Clear any pending interrupts
; Clear the ADC pair interrupts as well
; Enable the interrupt
; Save WO-W3 and SR registers
; Clear the interrupt
; ADBASE contains the encoded jump address
; within JMP_TBL
; Clear the IRQ flag in the ADC
; Actual Pair 0 Conversion Interrupt Handler
; Clear the IRQ flag in the ADC
; Actual Pair 1 Conversion Interrupt Handler
; Clear the IRQ flag in the ADC
; Clear the IRQ flag in the ADC
; Actual Pair 3 Conversion Interrupt Handler
; Clear the IRQ flag in the ADC
; Actual Pair 4 Conversion Interrupt Handler
; Actual Pair 2 Conversion Interrupt Handler
Preliminary
For example, if ADBASE is initialized with a value of
0x0360, a channel pair 1 interrupt would cause an
ADBASE
0b00000100). A channel pair 3 interrupt would cause
an ADBASE read value of 0x036C (0x360 +
0b00001100).
read
value
© 2006 Microchip Technology Inc.
of
0x0364
(0x360
+

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