DSPIC30F2020-30I/SP Microchip Technology Inc., DSPIC30F2020-30I/SP Datasheet - Page 138

• Manufacturer Part Number: DSPIC30F2020-30I/SP
• Description: DSP, 16-Bit, 12KB Flash, 512 RAM, 21 I/O, SDIP-28
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F2020-30I/SP

• A/d Inputs: 8-Channels, 10-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Ios: 21
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 28-pin SPDIP
• Programmable Memory: 12K Bytes
• Ram Size: 512 Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F1010/202X
12.31.2
If the OSYNC bit in the IOCONx register is set, the out-
put overrides performed via the OVRENH,L and the
OVDDAT<1:0> bits are synchronized to the PWM time
base. Synchronous output overrides occur when the
time base is zero.
If PTEN = 0, meaning the timer is not running, writes to
IOCON take effect on the next T
12.32 Functional Exceptions
12.32.1
All registers associated with the PWM module are reset
to the states given in Table 12-4 upon a Power-on
Reset. On a device reset, the PWM output pins are
tri-stated.
12.32.2
The selected Fault input pin has the ability to wake the
CPU from Sleep mode. The PWM module should gen-
erate an asynchronous interrupt if any of the selected
Fault pins is driven low while in Sleep.
It is recommended that the user disable the PWM out-
puts prior to entering Sleep mode. If the PWM module
is controlling a power conversion application, the action
of putting the device into Sleep will cause any control
loops to be disabled, and most applications will likely
experience issues unless they are explicitly designed
to operate in an Open-Loop mode.
DS70178C-page 136
OVERRIDE SYNCHRONIZATION
POWER RESET CONDITIONS
SLEEP MODE
CY
boundary.
Preliminary
12.32.3
The dsPIC30F202X module has a PTSIDL control bit in
the PTCON register. This bit determines if the PWM
module continues to operate or stops when the device
enters Idle mode. Stopped Idle mode functions like
Sleep mode, and Fault pins are asynchronously active.
• PTSIDL = 1 (Stop module when in Idle mode)
• PTSIDL = 0 (Don't stop module when in Idle
It is recommended that the user disable the PWM out-
puts prior to entering Idle mode. If the PWM module is
controlling a power-conversion application, the action
of putting the device into Idle will cause any control
loops to be disabled, and most applications will likely
experience issues unless they are explicitly designed
to operate in an Open-Loop mode.
12.33 Register Bit Alignment
Table 12-4 on page 142 shows the registers for the PS
PWM module. All time-based data for the module is
always bit-aligned with respect to time. For example: bit
3 in the period register, the duty cycle registers, the
dead-time registers, the trigger registers and the phase
registers always represents a value of 8.4 nsec,
assuming 30 MIPS operation. Unused portions of reg-
isters always read as zeros.
The use of data alignment makes it easier to write soft-
ware because it eliminates the need to shift time values
to fit into registers. It also eases the computation and
understanding of time allotment within a PWM cycle.
mode)
CPU IDLE MODE
© 2006 Microchip Technology Inc.