DSPIC30F2020-30I/SP Microchip Technology Inc., DSPIC30F2020-30I/SP Datasheet - Page 132
DSPIC30F2020-30I/SP
Manufacturer Part Number
DSPIC30F2020-30I/SP
Description
DSP, 16-Bit, 12KB Flash, 512 RAM, 21 I/O, SDIP-28
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F2023-30IPT.pdf
(286 pages)
Specifications of DSPIC30F2020-30I/SP
A/d Inputs
8-Channels, 10-Bit
Comparators
4
Cpu Speed
30 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Ios
21
Memory Type
Flash
Number Of Bits
16
Package Type
28-pin SPDIP
Programmable Memory
12K Bytes
Ram Size
512 Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
3-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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dsPIC30F1010/202X
EXAMPLE 12-1:
DS70178C-page 130
.
mov #0x0400, w0
mov w0, PTCON
; Set the PWM Period
mov #0x094D, w0
mov w0, PTPER
mov #0x0000, w0
mov w0, PHASE1
; Select individual Duty Cycle Control
mov #0x0001, w0
mov w0, PWMCON1
; Code for PWM Current Limit and Fault Inputs
mov #0x0003, w0
mov w0, FCLCON1
; Code for PWM Output Control
mov #0xC000, w0
mov w0, IOCON1
; Duty Cycle Setting
mov #0x04A6, w0
mov w0, PDC1
; Dead Time Setting
mov #0x0040, w0
mov w0, DTR1
mov w0, ALTDTR1
bset PTCON, #15
Note:
This code example does not illustrate configuration of various fault modes for the PWM module.
It is intended as a quick start guide for setting up the PWM Module.
CODE EXAMPLE FOR CONFIGURING PWM CHANNEL 1
; PWM Module is disabled, continue operation in
; idle mode, special event interrupt disabled,
; immediate period updates enabled, no external
; synchronization
; Select period to be approximately 2.5usec
; PLL Frequency is ~480MHz. This equates to a
; clocke period of 2.1nsec. The PWM period and
; duty cycle registers are triggered on both +ve
; and -ve edges of the PLL clock. Therefore,
; one count of the PTPER and PDCx registers
; equals 1.05nsec.
; So, to achieve a PWM period of 2.5usec, we
; choose PTPER = 0x094D
; no phase shift for this PWM Channel
; This register is used for generating variable
; phase PWM
; Fault interrupt disabled, Current Limit
; interrupt disabled, trigger interrupt,
; disabled, Primary time base provides timing,
; DC1 provides duty cycle information, positive
; dead time applied, no external PWM reset,
; Enable immediate duty cycle updates
; Disable current limit and fault inputs
; PWM1H and PWM1L is controlled by PWM module
; Output polarities are active high, override
; disabled
; To achieve a duty cycle of 50%, we choose
; the PDC1 value = 0.5*(PWM Period)
; The ON time for the PWM = 1.25usec
; The Duty Cycle Register will provide
; positive duty cycle to the PWMxH outputs
; when output polarities are active high
; (see IOCON1 register)
; Dead time ~ 67nsec
; Hex(40) = decimal(64)
; So, Dead time = 64*1.05nsec = 67.2nsec
; Note that the last 2 bits are unimplemented,
; therefore the dead time register can achieve a
; a resolution of about 4nsec.
; Load the same value in ALTDTR1 register
; turn ON PWM module
Preliminary
© 2006 Microchip Technology Inc.
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