IDT82V2084PFG8 IDT, Integrated Device Technology Inc, IDT82V2084PFG8 Datasheet - Page 44

• Manufacturer Part Number: IDT82V2084PFG8
• Description: IC LINE INTERFC UNIT 4CH 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2084PFG8

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1864-2; 82V2084PFG8

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-43 MAINT4: Maintenance Function Control Register 4
Table-44 MAINT5: Maintenance Function Control Register 5
Table-45 MAINT6: Maintenance Function Control Register 6
RIBLBA[7:0]
RIBLBD[7:0]
EXZ_DEF
ERR_SEL
CNT_TRF
ERR_INS
BPV_INS
CNT_MD
Symbol
Symbol
Symbol
-
(R/W, Address = 0EH,4EH,8EH,CEH)
(R/W, Address = 0FH,4FH,8FH,CFH)
(R/W, Address = 10H,50H,90H,D0H)
7-0
7-0
3-2
Bit
Bit
Bit
7
6
5
4
1
0
(000)00001 Defines the user-programmable receive Inband Loopback activate code. The default selection is 00001.
[phone] Defines the user-programmable receive Inband Loopback deactivate code. The default selection is 001001.
Default
Default
Default
00
0
0
0
0
0
0
These bits choose which type of error will be counted
RIBLBA[7:0] form the 8-bit repeating code
RIBLBA[6:0] form the 7-bit repeating code
RIBLBA[5:0] form the 6-bit repeating code
RIBLBA[4:0] form the 5-bit repeating code
RIBLBD[7:0] form the 8-bit repeating code
RIBLBD[6:0] form the 7-bit repeating code
RIBLBD[5:0] form the 6-bit repeating code
RIBLBD[4:0] form the 5-bit repeating code
Reserved.
BPV error insertion
A ‘0’ to ‘1’ transition on this bit will cause a single bipolar violation error to be inserted into the transmit data
stream. This bit must be cleared and set again for a subsequent error to be inserted.
PRBS/QRSS logic error insertion
A ‘0’ to ‘1’ transition on this bit will cause a single PRBS/QRSS logic error to be inserted into the transmit PRBS/
QRSS data stream. This bit must be cleared and set again for subsequent error to be inserted.
EXZ definition select
= 0: ANSI
= 1: FCC
= 00: the PRBS logic error is counted by a 16-bit error counter.
= 01: the EXZ error is counted by a 16-bit error counter.
= 10: the Received CV (BPV) error is counted by a 16-bit error counter.
= 11: both CV (BPV) and EXZ errors are counted by a 16-bit error counter.
Counter operation mode select
= 0: Manual Report Mode
= 1: Auto Report Mode
= 0: Clear this bit for the next ‘0’ to ‘1’ transition on this bit.
= 1: Error counting result is transferred to CNT0 and CNT1 and the error counter is reset.
44
Description
Description
Description
TEMPERATURE RANGES
INDUSTRIAL