IDT82V2084PFG8 IDT, Integrated Device Technology Inc, IDT82V2084PFG8 Datasheet - Page 42

• Manufacturer Part Number: IDT82V2084PFG8
• Description: IC LINE INTERFC UNIT 4CH 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2084PFG8

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1864-2; 82V2084PFG8

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-38 RCF2: Receiver Configuration Register 2
4.2.5
Table-39 MAINT0: Maintenance Function Control Register 0
UPDW[1:0]
PRBS_INV
SLICE[1:0]
PATT_CLK
PATT[1:0]
Symbol
Symbol
MG[1:0]
ATAO
AISE
LAC
NETWORK DIAGNOSTICS CONTROL REGISTERS
-
-
(R/W, Address =09H,49H,89H,C9H)
(R/W, Address = 0AH,4AH,8AH,CAH)
7-6
5-4
3-2
1-0
6-5
Bit
Bit
4
7
3
2
1
0
Default
Default
00
01
10
00
00
0
0
0
0
0
0
Receive slicer threshold
Equalizer observation window
Monitor gain setting: these bits select the internal linear gain boost
Selects reference clock for transmitting internal pattern
Reserved
= 00: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 40% of the peak amplitude.
= 01: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 50% of the peak amplitude.
= 10: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 60% of the peak amplitude.
= 11: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 70% of the peak amplitude.
= 00: 32 bits
= 01: 64 bits
= 10: 128 bits
= 11: 256 bits
= 00: 0 dB
= 01: 22 dB
= 10: 26 dB
= 11: 32 dB
Reserved
These bits select the internal pattern and insert it into the transmit data stream.
= 00: normal operation (PATT_CLK = 0) / insert all zeros (PATT_CLK = 1)
= 01: insert All Ones
= 10: insert PRBS (E1: 2
= 11: insert programmable Inband Loopback activate or deactivate code
= 0: uses TCLKn as the reference clock
= 1: uses MCLK as the reference clock
Inverts PRBS
= 0: PRBS data is not inverted
= 1: PRBS data is inverted before transmission and detection
The LOS/AIS criterion is selected as below:
= 0: G.775 (E1) / T1.231 (T1/J1)
= 1: ETSI 300233 & I.431 (E1) / I.431 (T1/J1)
AIS enable during LOS
= 0: AIS insertion on RDPn/RDNn/RCLKn is disabled during LOS
= 1: AIS insertion on RDPn/RDNn/RCLKn is enabled during LOS
Automatically Transmit All Ones (enabled only when PATT[1:0] = 01)
= 0: disabled
= 1: Automatically Transmit All Ones pattern at TTIPn/TRINGn during LOS.
15
-1) or QRSS (T1/J1: 2
42
20
Description
Description
-1)
TEMPERATURE RANGES
INDUSTRIAL