IDT82V2084PFG8 IDT, Integrated Device Technology Inc, IDT82V2084PFG8 Datasheet - Page 4

• Manufacturer Part Number: IDT82V2084PFG8
• Description: IC LINE INTERFC UNIT 4CH 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2084PFG8

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1864-2; 82V2084PFG8

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
4
5
6
7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
PROGRAMMING INFORMATION .............................................................................................. 34
4.1
4.2
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 54
5.1
5.2
TEST SPECIFICATIONS ............................................................................................................ 58
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 70
7.1
7.2
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 29
3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 29
3.8.2 ERROR DETECTION AND COUNTING ................................................................ 29
3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 30
LINE DRIVER FAILURE MONITORING ........................................................................... 30
MCLK AND TCLK ............................................................................................................. 31
3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 31
3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 31
MICROCONTROLLER INTERFACES ............................................................................. 32
3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 32
3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 32
INTERRUPT HANDLING .................................................................................................. 33
5V TOLERANT I/O PINS .................................................................................................. 33
RESET OPERATION ........................................................................................................ 33
POWER SUPPLY ............................................................................................................. 33
REGISTER LIST AND MAP ............................................................................................. 34
REGISTER DESCRIPTION .............................................................................................. 36
4.2.1 GLOBAL REGISTERS............................................................................................ 36
4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 37
4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 38
4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 40
4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 42
4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 45
4.2.7 LINE STATUS REGISTERS ................................................................................... 48
4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 51
4.2.9 COUNTER REGISTERS ........................................................................................ 52
4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 53
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 55
JTAG DATA REGISTER ................................................................................................... 55
5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 55
5.2.2 BYPASS REGISTER (BR)...................................................................................... 55
5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 55
5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 56
SERIAL INTERFACE TIMING .......................................................................................... 70
PARALLEL INTERFACE TIMING ..................................................................................... 71
4
TEMPERATURE RANGES
INDUSTRIAL