DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 9

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 4-2. Hardware Mode Block Diagram
5. CONTROL INTERFACE MODES
The DS325x devices can operate in hardware mode or two different CPU bus modes: 8-bit parallel and SPI serial.
In hardware mode, configuration input pins control device configuration, while status output pins indicate device
status. Internal registers are not accessible in hardware mode. The device is configured for hardware mode when
the HW pin is wired high (HW = 1).
In the CPU bus modes, most of the configuration and status pins used in hardware mode are reassigned to the
CPU bus interface. Through the bus interface an external processor can access a set of internal configuration and
status registers. A few configuration and status pins are active in both hardware mode and the CPU bus modes to
support specialized applications, such as protection switching. The device is configured for CPU bus mode when
the HW pin is wired low (HW = 0). The default CPU interface is 8-bit parallel. When the MOT, RD and WR pins are
all low and the ALE pin is high, the SPI interface is enabled. See Section
interfaces.
With the exception of the HW pin, configuration and status pins available in hardware mode have corresponding
register bits in the CPU bus mode. The hardware mode pins and the CPU bus mode register bits have identical
names and functions, with the exception that all register bits are active high. For example, LOS is indicated by the
receiver on the RLOS pin (active low) in hardware mode and the RLOS register bit (active high) in CPU bus mode.
The few configuration input pins that are active in CPU bus mode also have corresponding register bits. In these
cases, the actual configuration is the logical OR of pin assertion and register bit assertion. For example, the
transmitter output driver is tri-stated if the TTS pin is asserted (i.e., low) or the TTS register bit is asserted (high).
Figure 4-1
RXPn
RXNn
TDMn
TXPn
TXNn
and
VDD
VSS
Figure 4-2
Supply
Power
Analog
Local
Loopback
RMONn
TTSn
Monitor
Driver
show block diagrams of the DS325x in hardware mode and in CPU bus mode.
T3MCLK E3MCLK STMCLK
Loopback Control
LLBn
Automatic
Equalizer
Adaptive
Control
Gain
Adapter
+
ALOS
Clock
RLBn
squelch
master clock
TLBOn
Recovery
Clock &
Data
TCLKn
TJAn
RJAn
9 of 71
Digital
Local
Loopback
TBIN
Remote
Loopback
Encoder
B3ZS/HDB3
Digital LOS
B3ZS/
HDB3
Detector
Decoder
RLOSn
15
RBIN
for more information on the CPU
AIS, 100100…,
Configuration
PRBS Pattern
Generation
Global
TDSAn,
TDSBn
Detector
PRBS
Drivers,
Output
Clock
Invert
Clock
Invert
PRBSn
RTSn
RPOSn/RDATn
RNEGn/RLCVn
RCLKn
RCINV
HIZ
RST
HW
E3Mn
STSn
TPOSn/TDATn
TNEGn
TCLKn
TCINV
Semiconductor
DS325x
Dallas