DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 15

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. REGISTER DESCRIPTIONS
When the DS325x is configured in either of the two CPU bus modes (HW = 0), the registers shown in
are accessible through the CPU bus interfaces. All registers for the LIU ports are forced to their default values
during an internal power-on reset or when the RST pin is driven low. Setting an LIU’s RST bit high forces all
registers for that LIU to their default values. All register bits marked “—” must be written 0 and ignored when read.
The TEST registers must be left at their reset value of 00h for normal operation.
On the DS3253, only registers for LIUs 1, 2, and 3 are available. Writes into LIU 4 address space are ignored.
Reads from LIU 4 address space return all zeros. On the DS3252, address line A5 is not present, limiting the
address space to the LIU 1 and LIU 2 registers. On the DS3251, address lines A5 and A4 are not present, limiting
the address space to the LIU 1 registers.
Table 7-A. Register Map
Note 1: Underlined bits are read-only; all other bits are read-write.
Note 2: The registers are named REGn, where n = the LIU number (1, 2, 3, or 4). The register names are hyperlinks to the register descriptions.
Note 3: The bit names are the same for each LIU register set.
ADDRESS
09h–0Fh
19h–1Fh
29h–2Fh
39h–3Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
10h
11h
12h
13h
14h
15h
16h
17h
18h
20h
21h
22h
23h
24h
25h
26h
27h
28h
30h
31h
32h
33h
34h
35h
36h
37h
38h
Test Registers
Test Registers
Test Registers
Test Registers
REGISTER
RCVH1
RCVH2
RCVH3
RCVH4
RCVL1
RCVL2
unused
RCVL3
unused
RCVL4
unused
GCR1
SRIE1
CACR
GCR2
SRIE2
GCR3
SRIE3
GCR4
SRIE4
RCR1
RCR2
RCR3
RCR4
TCR1
SRL1
TCR2
SRL2
TCR3
SRL3
TCR4
SRL4
SR1
SR2
SR3
SR4
RCV[15]
RCV[15]
RCV[15]
RCV[15]
T3MOE
RCV[7]
RCV[7]
RCV[7]
RCV[7]
JAL[1]
JAFIE
JAL[1]
JAFIE
JAL[1]
JAFIE
JAL[1]
JAFIE
BIT 7
JAFL
JAFL
JAFL
JAFL
E3M
E3M
E3M
E3M
ITU
ITU
ITU
ITU
—
—
—
—
—
—
—
—
—
—
—
RCV[14]
RCV[14]
RCV[14]
RCV[14]
E3MOE
RCV[6]
RCV[6]
RCV[6]
RCV[6]
JAEIE
JAEIE
JAEIE
JAEIE
BIT 6
RBIN
JAEL
RBIN
JAEL
RBIN
JAEL
RBIN
JAEL
TBIN
TBIN
TBIN
TBIN
STS
STS
STS
STS
—
—
—
—
—
—
—
—
—
—
—
RCV[13]
RCV[13]
RCV[13]
RCV[13]
STMOE
15 of 71
RCV[5]
RCV[5]
RCV[5]
RCV[5]
RCINV
TDMIE
RCINV
TDMIE
RCINV
TDMIE
RCINV
TDMIE
TCINV
TCINV
TCINV
TCINV
TDML
TDML
TDML
TDML
BIT 5
TDM
TDM
TDM
TDM
LLB
LLB
LLB
LLB
LIU 1
LIU 2
LIU 3
LIU 4
—
—
—
—
—
—
—
RCV[12]
RCV[12]
RCV[12]
RCV[12]
PRBSIE
PRBSIE
PRBSIE
PRBSIE
PRBSL
PRBSL
PRBSL
PRBSL
RCV[4]
RCV[4]
RCV[4]
RCV[4]
PRBS
PRBS
PRBS
PRBS
BIT 4
RLB
RJA
RLB
RJA
RLB
RJA
RLB
RJA
TJA
TJA
TJA
TJA
—
—
—
—
—
—
—
—
PBERIE
RCV[11]
PBERIE
RCV[11]
PBERIE
RCV[11]
PBERIE
RCV[11]
PBERL
PBERL
PBERL
PBERL
RCV[3]
RCV[3]
RCV[3]
RCV[3]
TDSA
TDSA
TDSA
TDSA
BIT 3
RPD
RPD
RPD
RPD
TPD
TPD
TPD
TPD
—
—
—
—
—
—
—
—
—
—
—
—
AMCSEL[1] AMCSEL[0]
RCV[10]
RCV[10]
RCV[10]
RCV[10]
RCV[2]
RCV[2]
RCV[2]
RCV[2]
RCVIE
RCVIE
RCVIE
RCVIE
TDSB
RCVL
TDSB
RCVL
TDSB
RCVL
TDSB
RCVL
BIT 2
RTS
RTS
RTS
RTS
TTS
TTS
TTS
TTS
—
—
—
—
—
—
—
—
—
—
—
RLOLIE
RLOLIE
RLOLIE
RLOLIE
RLOLL
RCV[1]
RCV[9]
RLOLL
RCV[1]
RCV[9]
RLOLL
RCV[1]
RCV[9]
RLOLL
RCV[1]
RCV[9]
RMON
RMON
RMON
RMON
TLBO
RLOL
TLBO
RLOL
TLBO
RLOL
TLBO
RLOL
BIT 1
—
—
—
—
—
—
—
—
—
—
—
Table 7-A
RLOSIE
AMCEN
RLOSIE
RLOSIE
RLOSIE
RCVUD
RCVUD
RCVUD
RCVUD
RLOSL
RCV[0]
RCV[8]
RLOSL
RCV[0]
RCV[8]
RLOSL
RCV[0]
RCV[8]
RLOSL
RCV[0]
RCV[8]
JAL[0]
JAL[0]
JAL[0]
JAL[0]
RLOS
RLOS
RLOS
RLOS
BIT 0
RST
RST
RST
RST
—
—
—
—
—
—
—