DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 12

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6-D. Hardware Mode Pin Descriptions
Note: These pins are active in hardware mode.
RMONn
TDSAn,
TDSBn
RCINV
TLBOn
TCINV
NAME
E3Mn
LLBn,
STSn
RLBn
RBIN
RJAn
TBIN
TJAn
TYPE
I
I
I
I
I
I
I
I
I
I
I
I
E3 Mode Enable
0 = DS3 operation
1 = E3 or STS-1 operation
STS-1 Mode Enable
When E3M = 1,
When E3M = 0, STS selects the DS3 AIS pattern. See
Local Loopback Select, Remote Loopback Select
{LLB, RLB} =
Receiver Binary Framer-Interface Enable
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is
disabled.
1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code
violations. The B3ZS/HDB3 encoder is enabled.
Receiver Clock Invert
0 = RPOS/RDAT and RNEG/RLCV update on the falling edge of RCLK.
1 = RPOS/RDAT and RNEG/RLCV update on the rising edge of RCLK.
Receiver Jitter Attenuator Enable
0 = remove jitter attenuator from the receiver path
1 = insert jitter attenuator into the receiver path
See
Receive Monitor-Preamp Enable. RMON determines whether or not the receiver’s preamp is enabled
to provide flat gain to the incoming signal before the AGC/equalizer block processes it. This feature
should be enabled when the device is being used to monitor signals that have been resistively
attenuated by a monitor jack. See Section
0 = disable the monitor preamp
1 = enable the monitor preamp
Transmitter Binary Framer-Interface Enable
0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is
disabled.
1 = Transmitter framer interface is binary on the TDAT pin. (TNEG is ignored and should be wired low.)
The B3ZS/HDB3 encoder is enabled.
Transmitter Clock Invert
0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK.
1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK.
Transmitter Data Select. These inputs select the source of the transmit data. See
details.
Transmitter Jitter Attenuator Enable
0 = remove jitter attenuator from the transmitter path
1 = insert jitter attenuator into the transmitter path
See
Transmitter Line Build-Out Enable. TLBO indicates cable length for waveform shaping in DS3 and
STS-1 modes. TLBO is ignored for E3 mode and should be wired high or low.
0 = cable length ≥ 225ft
1 = cable length < 225ft
Table 6-I
Table 6-I
0 = E3 operation
1 = STS-1 operation
for more information.
for more information.
00 = no loopback
01 = remote loopback
10 = analog local loopback
11 = digital local loopback
12 of 71
8.2
FUNCTION
for more information.
Table
6-G.
Table 6-G
for