DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 5

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FEATURES (CONTINUED)
Receiver
Transmitter
Jitter Attenuator
Clock Adapter
Parallel CPU Interface
SPI CPU Interface
AGC/equalizer block handles from 0 to 15dB of cable loss
Loss-of-lock (LOL) PLL status indication
Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp
Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775)
Optional B3ZS/HDB3 decoder
Line-code violation output pin and counter
Binary or bipolar framer interface
On-board 2
Clock inversion for glueless interfacing
Tri-state clock and data outputs support protection switching applications
Per-channel power-down control
Binary or bipolar framer interface
Gapped clock capable up to 51.84MHz
Wide 50 ± 20% transmit clock duty cycle
Clock inversion for glueless interfacing
Optional B3ZS/HDB3 encoder
On-board 2
Complete DS3 AIS generator (ANSI T1.107)
Unframed all-ones generator (E3 AIS)
Line build-out (LBO) control
Tri-state line driver outputs support protection switching applications
Per-channel power-down control
Output driver monitor
On-chip crystal-less jitter attenuator
Meets all applicable ANSI, ITU, ETSI and Telcordia jitter transfer and output jitter requirements
Can be placed in the transmit path, receive path or disabled
Selectable FIFO depth: 16, 32, 64 or 128 bits
Overflow and underflow status indications
Operates from a single DS3, E3, STS-1, 19.44 MHz, 38.88 MHz, or 77.76 MHz master clock
Synthesizes clock rates that are not provided externally
Use of common system timing frequencies such as 19.44 MHz eliminates the need for any local oscillators,
reduces cost and board space
Very small jitter gain and intrinsic jitter generation
Optionally provides synthesized clocks on output pins for use by neighboring components, such as framers or
mappers
Multiplexed or nonmultiplexed 8-bit interface
Configurable for Intel mode (CS, WR, RD) or Motorola mode (CS, DS, R/W)
Operation up to 10 Mbit/s
Burst mode for multi-byte read and write accesses
Programmable clock polarity and phase
Half-duplex operation gives option to tie SDI and SDO together externally to reduce wire count
15
15
- 1 and 2
- 1 and 2
23
23
- 1 PRBS detector
- 1 PRBS generator
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