DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 28

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4 Waveshaping, Line Build-Out, Line Driver
The waveshaping block converts the transmit clock, positive data, and negative data signals into a single AMI
signal with the waveshape required for interfacing to DS3/E3/STS-1 lines.
9-1
Because DS3 and STS-1 signals must meet the waveform templates at the cross-connect through any cable length
from 0 to 450ft, the waveshaping circuitry includes a selectable LBO feature. For cable lengths of 225ft or greater,
the TLBO pin (hardware mode) or the TLBO configuration bit in the
When TLBO is low, output pulses are driven onto the coaxial cable without any preattenuation. For cable lengths
less than 225ft, TLBO should be high to enable the LBO circuitry. When TLBO is high, pulses are preattenuated by
the LBO circuitry before being driven onto the coaxial cable. The LBO circuitry provides attenuation that mimics the
attenuation of 225ft of coaxial cable.
The transmitter line driver can be disabled and the TXP and TXN outputs tri-stated by asserting the TTS input or
the TTS configuration bit in the
the
9.5 Interfacing to the Line
The transmitter interfaces to the outgoing DS3/E3/STS-1 coaxial cable (75Ω) through a 2:1 step-down transformer
connected to the TXP and TXN pins.
recommended interface components.
9.6 Transmit Driver Monitor
The transmit driver monitor compares the amplitude of the transmit waveform to thresholds V
the amplitude is less than V
activates the TDM output pin (hardware mode or CPU bus mode) or sets the TDM status bit in the
optionally activates the INT output (CPU bus mode). When the transmitter is tri-stated, the transmit driver monitor is
also disabled.
Note that the transmit driver monitor can be affected by reflections caused by shorts and opens on the line. A short
at a distance less than a few inches (~11 inches for FR4 material) can introduce inverted reflections that reduce the
outgoing pulse amplitude below the V
Similarly an open circuit a similar distance away can introduce noninverted reflections that increase the outgoing
amplitude above the V
away from TXP/TXN can also activate TDM and/or TDM, but this effect is data-pattern dependent.
9.7 Transmitter Power-Down
To minimize power consumption when the transmitter is not being used, assert the TPD configuration bit in the
TCR
high-impedance state and the transmit amplifiers are powered down.
9.8 Transmitter Jitter Generation (Intrinsic)
The transmitter meets the jitter generation requirements of all applicable standards, with or without the jitter
attenuator enabled.
9.9 Transmitter Jitter Transfer
Without the jitter attenuator enabled in the transmit side, the transmitter passes jitter through unchanged. With the
jitter attenuator enabled in the transmit side, the transmitter meets the jitter transfer requirements of all applicable
telecommunication standards in
TCR
show the waveform template specifications and test parameters.
register (CPU bus mode only). When the transmitter is powered down, the TXP and TXN pins are put in a
register (CPU bus mode) also tri-states the TXP and TXN outputs.
TXMAX
threshold and thereby activate TDM and/or TDM. Shorts and opens at larger distances
TXMIN
Table
TCR
or greater than V
register. Powering down the transmitter through the TPD configuration bit in
Table 14-A
1-A. See
TXMIN
Figure 2-1
threshold and thereby activate the TDM pin and/or TDM status bit.
Figure
specifies the required characteristics of the transformer.
TXMAX
28 of 71
10-1.
shows the arrangement of the transformer and other
for approximately 32 MCLK cycles, then the monitor
TCR
register (CPU bus mode) should be low.
Table 9-A
through
Table 9-E
TXMIN
SR
and V
register and
and
TXMAX
Figure
. If