DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 24

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS3251/DS3252/DS3253/DS3254
8. RECEIVER
8.1 Interfacing to the Line
The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the receiver interfaces to the
incoming coaxial cable (75Ω) through a 1:2 step-up transformer.
Figure 2-1
shows the arrangement of the
transformer and other recommended interface components.
Table 14-A
specifies the required characteristics of the
transformer. The receiver expects the incoming signal to be in B3ZS- or HDB3-coded AMI format.
8.2 Optional Preamp
The receiver can be used in monitoring applications, which typically have series resistors with a resistive loss of
approximately 20dB. When the RMON input pin is high (hardware mode) or RCR:RMON=1 (CPU bus mode), the
receiver compensates for this resistive loss by applying approximately 14dB of flat gain to the incoming signal
before sending the signal to the AGC/equalizer block, where additional flat gain is applied as need.
8.3 Automatic Gain Control (AGC) and Adaptive Equalizer
The AGC circuitry applies flat (frequency independent) gain to the incoming signal to compensate for flat losses in
the transmission channel and variations in transmission power. Since the incoming signal also experiences
frequency-dependent losses as it passes through the coaxial cable, the adaptive equalizer circuitry applies
frequency-dependent gain to offset line losses and restore the signal. The AGC/equalizer circuitry automatically
adapts to coaxial cable losses from 0 to 15dB, which translates into 0 to 380 meters (DS3), 0 to 440 meters (E3), or
0 to 360 meters (STS-1) of coaxial cable (AT&T 734A or equivalent). The AGC and the equalizer work
simultaneously but independently to supply a signal of nominal amplitude and pulse shape to the clock and data
recovery block. The AGC/equalizer block automatically handles direct (0 meters) monitoring of the transmitter
output signal.
8.4 Clock and Data Recovery (CDR)
The CDR block takes the amplified, equalized signal from the AGC/equalizer block and produces separate clock,
positive data, and negative data signals. The CDR operates from the LIU’s master clock. See Section
12
for more
information about master clocks and clock selection.
The receiver locks onto the incoming signal using a clock recovery PLL. The status of the PLL lock is indicated in
the RLOL status bit in the
SR
register. The RLOL bit is set when the difference between recovered clock frequency
and MCLK frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. A change of
state of the RLOL status bit can cause an interrupt on the INT pin if enabled to do so by the RLOLIE interrupt-
enable bit in the
SRIE
register. Note that if the master clock is not present, RLOL is not set.
8.5 Loss-of-Signal (LOS) Detector
The receiver contains analog and digital LOS detectors. The analog LOS detector resides in the AGC/equalizer
block. If the incoming signal level is less than a signal level approximately 24dB below nominal, analog LOS
(ALOS) is declared. The ALOS signal cannot be directly examined, but when ALOS occurs the AGC/equalizer
mutes the recovered data, forcing all zeros out of the data recovery circuitry and causing digital LOS (DLOS),
which is indicated by the RLOS pin and the RLOS status bit in the
SR
register. ALOS clears when the incoming
signal level is greater than or equal to a signal level approximately 18 dB below nominal.
The digital LOS detector declares DLOS when it detects 175 ± 75 consecutive zeros in the recovered data stream.
When DLOS occurs, the receiver asserts the RLOS pin (hardware mode) or the RLOS status bit (CPU bus mode).
DLOS is cleared when there are no EXZ occurrences over a span of 175 ±75 clock periods. An EXZ occurrence is
defined as three or more consecutive zeros in the DS3 and STS-1 modes and four or more consecutive zeros in
the E3 mode. The RLOS pin and the RLOS status bit are deasserted when the DLOS condition is cleared. In CPU
bus mode, a change of the RLOS status bit can cause an interrupt on the INT pin if enabled to do so by the
RLOSIE interrupt-enable bit in the
SRIE
register.
The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector, which
asserts RLOS when it counts 175 ±75 consecutive zeros coming out of the CDR block and clears RLOS when it
counts 175 ±75 consecutive pulse intervals without excessive zero occurrences.
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