DSPIC30F3014-30I/P Microchip Technology Inc., DSPIC30F3014-30I/P Datasheet - Page 18
DSPIC30F3014-30I/P
Manufacturer Part Number
DSPIC30F3014-30I/P
Description
DSP, 16-Bit, 24 KB Flash, 2KB RAM, 30 I/O, PDIP-40
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F3014-30IP.pdf
(220 pages)
Specifications of DSPIC30F3014-30I/P
A/d Inputs
13-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
30
Interface
CAN, I2C, SPI, UART/USART
Ios
30
Memory Type
Flash
Number Of Bits
16
Package Type
40-pin PDIP
Programmable Memory
24K Bytes
Ram Size
2K Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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dsPIC30F3014/4013
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
1.
2.
3.
4.
5.
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
DS70138E-page 16
DIVF
DIV.sd
DIV.s
DIV.ud
DIV.u
DIVF – 16/16 signed fractional divide
DIV.sd – 32/16 signed divide
DIV.ud – 32/16 unsigned divide
DIV.s– 16/16 signed divide
DIV.u – 16/16 unsigned divide
Instruction
Divide Support
DIVIDE INSTRUCTIONS
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm/Wn → W0; Rem → W1
Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Unsigned divide: Wm/Wn → W0; Rem → W1
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion, as shown in Table 2-1 (REPEAT will execute the
target instruction {operand value+1} times). The
REPEAT loop count must be setup for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
Function
Note:
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
© 2007 Microchip Technology Inc.
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