DSPIC30F3014-30I/P Microchip Technology Inc., DSPIC30F3014-30I/P Datasheet - Page 121
DSPIC30F3014-30I/P
Manufacturer Part Number
DSPIC30F3014-30I/P
Description
DSP, 16-Bit, 24 KB Flash, 2KB RAM, 30 I/O, PDIP-40
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F3014-30IP.pdf
(220 pages)
Specifications of DSPIC30F3014-30I/P
A/d Inputs
13-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
30
Interface
CAN, I2C, SPI, UART/USART
Ios
30
Memory Type
Flash
Number Of Bits
16
Package Type
40-pin PDIP
Programmable Memory
24K Bytes
Ram Size
2K Bytes
Timers
3-16-bit, 1-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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18.3.7
The DCI module has a dedicated 12-bit time base that
produces the bit clock. The bit clock rate (period) is set
by writing a non-zero 12-bit value to the BCG<11:0>
control bits in the DCICON3 SFR.
When the BCG<11:0> bits are set to zero, the bit clock
is disabled. If the BCG<11:0> bits are set to a non-zero
value, the bit clock generator is enabled. These bits
should be set to ‘0’ and the CSCKD bit set to ‘1’ if the
serial clock for the DCI is received from an external
device.
The formula for the bit clock frequency is given in
Equation 18-2.
TABLE 18-1:
© 2007 Microchip Technology Inc.
Note 1:
F
S
44.1
(KHz)
12
32
48
2:
8
When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the
operation of the DCI module.
When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must
meet the device timing requirements.
BIT CLOCK GENERATOR
DEVICE FREQUENCIES FOR COMMON CODEC CSCK FREQUENCIES
F
CSCK
256
256
32
32
64
/F
S
F
CSCK
1.4112
2.048
3.072
1.024
3.072
(MHz)
(1)
F
OSC
5.6448
8.192
6.144
8.192
6.144
EQUATION 18-2:
The required bit clock frequency is determined by the
system sampling rate and frame size. Typical bit clock
frequencies range from 16x to 512x the converter
sample rate depending on the data converter and the
communication protocol that is used.
To achieve bit clock frequencies associated with
common audio sampling rates, the user needs to select
a crystal frequency that has an ‘even’ binary value.
Examples of such crystal frequencies are listed in
Table 18-1.
(MH
dsPIC30F3014/4013
Z
)
PLL
F
16
4
8
8
8
BCK
=
BIT CLOCK FREQUENCY
2 (BCG + 1)
•
F
F
CY
11.2896
12.288
16.384
24.576
CY
8.192
(MIPS)
DS70138E-page 119
BCG
1
1
7
3
3
(2)
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