CY7C924ADX-AXC Cypress Semiconductor Corp, CY7C924ADX-AXC Datasheet - Page 42

• Manufacturer Part Number: CY7C924ADX-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transceiverr

Specifications of CY7C924ADX-AXC

• Package / Case: 100-LQFP
• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 622 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage (typ): 5V
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• No. Of Receivers: 2
• Frequency Max: 50MHz
• Rohs Compliant: Yes
• Termination Type: SMD
• Filter Terminals: SMD
• Driver Case Style: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-2918; CY7C924ADX-AXC

associated data), the characters associated with the atomic
operation are discarded and not written to the Receive FIFO.
Upon internal recognition of RXBISTEN*, the serial address
match flag is cleared such that once BIST has been disabled and
data is again being received, all received data is rejected until a
new serial address is again received that matches the address
match criteria.
Note. If the CY7C924ADX is set to match all data (all 1s in the
multicast match field), then it is not necessary to get an address
match before receiving data following the termination of BIST. On
reset or when programmed to this state, the device ignores all
serial address commands and matches all data.
Any data present in the Receive FIFO when RXBISTEN* is
recognized remains in the FIFO and cannot be read until the
BIST operation is complete. The data in the Receive FIFO
remains valid, but is NOT available for reading through the host
parallel interface. This is because the error output indicator for
receive BIST operations is the RXRVS signal, which is normally
part of the RXDATA bus. To prevent read operations while BIST
is in operation, the RXEMPTY* and RXHALF* flags are forced to
indicate an Empty condition. Once RXBISTEN* has been
removed and recognized internally, the Receive FIFO status
flags are updated to reflect the current content status of the
Receive FIFO.
To allow removal of stale data from the Receive FIFO, it may be
reset during a BIST operation. The reset operation proceeds as
documented, with the exception that the RXEMPTY* and
RXHALF* status flags already indicate an empty condition. The
RXFULL* flag is used to present BIST progress. The active state
on RXFULL* and RXEMPTY* flags remain controlled by the
present operating mode and interface timing model (UTOPIA or
Cascade) as selected by EXTFIFO*.
When RXBISTEN* has been recognized, RXFULL* becomes the
receive BIST loop indicator, regardless of the logic state of
FIFOBYP*. When RXBISTEN* is first recognized with the
Receive FIFO enabled, the RXFULL* flag is clocked to a set
state, regardless of the addressed state of the Receive FIFO (if
AM* is sampled LOW or not). Following this, RXFULL* remains
set until the receiver detects the start of the BIST pattern. Then
RXFULL* is deasserted for the duration of the BIST pattern,
pulsing asserted for one RXCLK period on the last symbol of
each BIST loop. If 14 of 28 consecutive characters are received
in error, RXFULL* returns to the set state until the start of a BIST
sequence is again detected.
Just like the BIST status flag on the transmit data path, when the
Receive FIFO is enabled the RXFULL* flag captures the
asserted states, and keeps them until they are read. This means
that if the status flag is not read on a regular basis, events may
be lost.
The detection of errors is presented on the RXRVS output.
Unlike the RXFULL* FIFO status flag, the active state of this
output is not controlled by the EXTFIFO input. With the Receive
FIFO enabled, these outputs should operate the same as the
RXFULL* flag, with respect to preserving the detection state of
an error until it is read.
Unlike the RXFULL* flag, which only needs the CY7C924ADX to
be addressed (AM* sampled LOW by RXCLK) to enable the
RXFULL* three-state driver, and an RXCLK to “read” the flag, the
RXRVS output requires a selection (assertion of RXEN* while
Document #: 38-02008 Rev. *G
addressed) to enable the RXDATA bus three-state drivers. The
selection process is necessary to ensure that a multi-PHY imple-
mentation does not enable multiple RXRVS drivers at the same
time.
When the Receive FIFO is bypassed, the interface is clocked by
the RXCLK output signal. While the active or asserted state of
the RXFULL* signal is still controlled by the EXTFIFO input, the
state of any completed BIST loops or detected errors are no
longer preserved. Instead, the RXFULL* flag reflects the
dynamic state of the BIST loop progress, and is asserted only
once every 511 character periods. If the interface is not
addressed at the time that this occurs, then the FIFO status flags
remain in a High-Z state and the loop event is lost. This is also
true of the RXRVS output, such that if the CY7C924ADX receive
path is not selected to enable the RXDATA bus three-state
drivers, the detection of a BIST miscompare is lost.
BIST Three-state Control
When BIST is enabled on either the transmitter or the receiver,
the three-state enable signals for the BIST status flags and error
indicators work the same as for normal data processing. The
output drivers for the BIST status that is presented on FIFO
status flags are only enabled when AM* has been sampled
asserted (LOW) by the respective clock (TXCLK, RXCLK, or
REFCLK).
To access the BIST error information, it is necessary to perform
a read cycle of the addressed receiver. This means that AM*
must be LOW to allow a receiver address match (Rx_Match) to
exist, and RXEN* must then be asserted to select the device.
Because the part is in BIST, no data is read from the FIFO, but
the data bus is driven. This allows the RXRVS indicator to be
driven onto the RXDATA bus. So long as RXEN* remains
asserted, the receiver stays selected, the data bus remains
driven, and RXRVS has meaning.
Bus Interfacing
The parallel transmit and receive host interfaces to the
CY7C924ADX are configurable for either synchronous or
asynchronous operation. Each of these configurations supports
two selectable timing and control models of UTOPIA or Cascade.
All asynchronous bus configurations have the internal Transmit
and Receive FIFOs enabled. This allows data to be written or
read from these FIFOs at any rate up to the maximum 50-MHz
clock rate of the FIFOs. All internal operations of the
CY7C924ADX do not use the external TXCLK or RXCLK, but
instead make use of synthesized derivatives of REFCLK for
transmit path operations and a recovered character clock for
receive path operations.
All synchronous bus configurations require the bus interface
operations to be synchronous to REFCLK on the transmit path
and the recovered clock (output as RXCLK) on the receive path.
The internal FIFOs are bypassed in all synchronous modes.
The two supported timing and control models are UTOPIA and
Cascade. These timing models take their name from their default
configuration. The UTOPIA timing model is based on the ATM
Forum UTOPIA interface standards. This timing model is that of
a FIFO with active LOW FIFO status flags and read/write
enables.
CY7C924ADX
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