CY7C924ADX-AXC Cypress Semiconductor Corp, CY7C924ADX-AXC Datasheet - Page 21

• Manufacturer Part Number: CY7C924ADX-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transceiverr

Specifications of CY7C924ADX-AXC

• Package / Case: 100-LQFP
• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 622 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage (typ): 5V
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• No. Of Receivers: 2
• Frequency Max: 50MHz
• Rohs Compliant: Yes
• Termination Type: SMD
• Filter Terminals: SMD
• Driver Case Style: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-2918; CY7C924ADX-AXC

(K28.0) Special Character code is inserted before the data
character with which TXINT is associated is sent. When TXINT
transitions from 1→0, a C3.0 (K28.3) Special Character code is
sent. The reception of these characters generates an equivalent
action on the attached receiver’s RXINT status output.
The combination of RXHALF*, TXINT, RXINT, and TXHALT* may
be used to prevent a remote FIFO overflow, which would result
in lost data. This back pressure mechanism can significantly
improve data integrity in systems that cannot guarantee the full
bandwidth of the host system at all times.
Elasticity Buffer
There is a short (8 character) FIFO between the receive and
transmit paths. This FIFO separates the time domains of the
received serial data stream and the outbound transmit data
stream. This permits retransmission of received data without
worry of jitter gain or jitter transfer. This allows error free trans-
mission of the same data, when configured in daisy chain or ring
configurations, to an unlimited number of destinations.
This Elasticity Buffer is enabled when the LOOPTX input is
asserted HIGH. This directs the receiver to place all non-C5.0
(K28.5) characters into the Elasticity Buffer. LOOPTX also
directs the Transmit Control State Machine to read data from the
Elasticity Buffer instead of from the Transmit FIFO.
While retransmitting data from the Elasticity Buffer, the Transmit
FIFO is available to preload data to be transmitted. Once
LOOPTX is deasserted (LOW), normal data transmission from
the Transmit FIFO resumes.
This LOOPTX capability is only possible when sending 8 bit
encoded data streams. It cannot be used with byte-packed or
nonencoded data streams, and requires that the Transmit and
Receive FIFOs are enabled. The receiver must also be
configured to process embedded commands (receiver Discard
Policy cannot be 0). The reclocked connection may be required
when sending non-8B/10B coded data streams, or data streams
that cannot tolerate the data forwarding policies of the Elasticity
Buffer.
Serial Line Receivers
Two differential line receivers, INA± and INB±, are available to
accept serial data streams, with the active input selected using
the A/B* input. The DLB[1:0] inputs allow the transmit Serializer
output to be selected as a third input serial stream, but this path
is generally used only for diagnostic purposes. The serial line
receiver inputs are all differential, and will accommodate wire
interconnect with filtering losses or transmission line attenuation
greater than 9 dB (V
differential) or can be directly connected to +5 V fiber optic
interface modules (any ECL logic family, not limited to ECL
100K). The common-mode tolerance of these line receivers
accommodates a wide range of signal termination voltages.
As can be seen in
configured to allow single-pin control for most applications. For
those systems requiring selection of only INA± or INB±, the
DLB[1:0] signals can be tied LOW, and the A/B selection can be
performed using only A/B*. For those systems requiring only a
single input and a local loopback, the A/B* can be tied HIGH or
Document #: 38-02008 Rev. *G
DIFF
Table 3
> 200 mV, or 400 mV peak-to-peak
on page 18, these inputs are
LOW, DLB[1] signal can be tied LOW and DLB[0] can be used
for loopback control.
Signal Detect
The selected Line Receiver (that routed to the clock and data
recovery PLL) is simultaneously monitored for:
■
■
■
■
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFI* (Link Fault Indicator) output, which changes
synchronous to RXCLK. While link status is monitored internally
at all times, it is necessary to have transitions on RXCLK to allow
this signal to change externally.
Clock/Data Recovery
The extraction of a bit rate clock and recovery of data bits from
the received serial stream is performed within the Clock/Data
Recovery (CDR) block. The clock extraction function is
performed by a high performance embedded phase locked loop
(PLL) that tracks the frequency of the incoming bit stream and
aligns the phase of its internal bit rate clock to the transitions in
the serial data stream.
The CDR makes use of the clock present at the REFCLK input.
It ensures that the VCO (within the CDR) is operating at the
correct frequency (rather than some harmonic of the bit rate), to
improve PLL acquisition time, and to limit unlocked frequency
excursions of the CDR VCO when no data is present at the serial
inputs.
Regardless of the type of signal present, the CDR will attempt to
recover a data stream from it. If the frequency of the recovered
data stream is outside the limits for the range controls, the CDR
PLL will track REFCLK instead of the data stream. When the
frequency of the selected data stream returns to a valid
frequency, the CDR PLL is allowed to track the received data
stream. The frequency of REFCLK must be within ±400 ppm of
the frequency of the clock that drives the REFCLK signal at the
remote transmitter to ensure a lock to the incoming data stream.
For systems using multiple or redundant connections, the LFI*
output can select an alternate data stream. When an LFI*
indication is detected, external logic can toggle selection of the
INA± and INB± inputs through the A/B* input. When a port switch
takes place, the PLL must reacquire the new serial stream and
frame the incoming characters.
Clock Divider
This block contains the clock division logic, used to transfer the
data from the Deserializer/Framer to the Decoder once every
character (once every ten or twelve bits) clock. This counter is
free running and generates outputs at the bit rate divided by 10
(12 when the BYTE8/10* and ENCBYP* are LOW). When the
Receive FIFO is bypassed, one of these generated clocks is
driven out the RXCLK pin.
Analog amplitude (>400 mV
Transition density
Received data stream outside normal frequency range
(±400 ppm)
Detected carrier.
DIFF
pk-pk)
CY7C924ADX
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