CY7C924ADX-AXC Cypress Semiconductor Corp, CY7C924ADX-AXC Datasheet - Page 39

• Manufacturer Part Number: CY7C924ADX-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transceiverr

Specifications of CY7C924ADX-AXC

• Package / Case: 100-LQFP
• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 622 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage (typ): 5V
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• No. Of Receivers: 2
• Frequency Max: 50MHz
• Rohs Compliant: Yes
• Termination Type: SMD
• Filter Terminals: SMD
• Driver Case Style: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-2918; CY7C924ADX-AXC

Output Register Mapping
The RXDATA[11:0] output bus is mapped into a character
consisting of eight bits of data, one bit that carries violation infor-
mation, and an RXSC/D* bit that identifies the character as either
control or data.
These bits have combinations that identify the meaning of the
remaining bits of the character. If RXRVS is HIGH and RXSC/D*
is HIGH the decoder outputs a C0.7, C1.7, C2.7 or C4.7 in
response to reception of either an SVS (C0.7) character or other
invalid character.
Synchronous Undecoded
In this mode, both the Receive FIFO and the 10B/8B Decoder
are bypassed (FIFOBYP* and ENCBYP* are LOW), and data
passes directly from the Deserializer to the output register. The
Deserializer operates synchronous to the recovered bit-clock,
which is divided by 10 or 12 to generate the output RXCLK clock.
In this mode the RXRST* input is not interpreted and may be
biased either HIGH or LOW.
This mode is usually used for products containing external
decoders or descramblers that must meet specific protocol
requirements. New data is provided at the RXDATA outputs once
every rising edge of RXCLK. Received characters are not
checked for any specific coding requirements and no decoding
errors are reported.
Asynchronous Decoded
Asynchronous Decoded mode is the most powerful operating
mode of the CY7C924ADX HOTLink Receiver. Both the Receive
FIFO and the Decoder are enabled (FIFOBYP* and ENCBYP*
are HIGH). This allows reception of normal data streams, while
offering the added benefits of embedded cell markers, an
expanded command set, serial address support, and in-band
bypass-signaling (for flow control or other purposes). All
characters added to the data stream by the transmitter to support
these additional capabilities may be automatically extracted by
the Receive Control State Machine in the CY7C924ADX Trans-
ceiver.
The deserializer operates synchronous to the recovered
bit-clock, which is divided by 10 to generate the Receive FIFO
write clock. When the Receive FIFO is addressed by AM* and
selected by RXEN*, characters are read from the FIFO using the
external RXCLK input.
Asynchronous Decoded mode support the same Output
Register mapping as the Synchronous Decoded mode. Because
both the Receive FIFO and Decoder are enabled, the output
FIFO may be read at any rate supported by the FIFO (0 to
50MHz), however, if the Receive FIFO ever indicates a full condi-
tion (RXFULL* is asserted), data may be lost.
Embedded Cell Marker
An embedded cell marker is used to mark the start of cells or
frames of information passed from one end of the link to the
other. When a C8.0 (K23.7) character is detected in the data
stream, the next character is written to the Receive FIFO along
with RXSOC set HIGH, and RXSC/D* and RXRVS set LOW.
When the character accompanying this marker is read from the
Document #: 38-02008 Rev. *G
Receive FIFO with these same bits set, it indicates the start of a
cell or frame.
Expanded Command
The standard 8B/10B Character set contains all 256 possible
data characters, but only twelve Special Character codes. To
allow use of a larger selection of command codes, one Special
Character code was selected to expand the command set.
An Expanded Command marker is used to mark the associated
data as any one of 256 (2
C9.0 (K27.7) character is detected in the data stream, the
following character is written to the Receive FIFO along with both
RXSOC and RXSC/D* set HIGH, and RXRVS set LOW. When
the character accompanying this marker is read from the
Receive FIFO with these same bits set, it may be used to indicate
that the data on the RXDATA bus is an Expanded Command.
Serial Addressing
The CY7C924ADX receive path can be directed to accept all
characters, or to only accept that data specifically addressed to
it. This address control is managed through an embedded
Address Compare Register in the receiver logic. This register
supports either domain (multicast) or exact-match (unicast)
based compares on an address field received across the serial
link. When a C10.0 (K29.7) special code is received, the immedi-
ately following data character contains the address field that is
compared with the receiver Serial Address Register contents.
When the CY7C924ADX is configured for multicast address
matching, the received address field is compared as an OR of a
bit-wise AND with the Serial Address Register. A valid match
between any of the bits sets the switch to allow the following data
to be written into the Receive FIFO. If no matches are found, the
data is not written to the Receive FIFO and is discarded.
When the CY7C924ADX is configured for unicast address
matching, the received address field is compared for an exact
match with the Serial Address Register. If an exact match is
found, a switch is set in the receiver to accept all following data
until the next serial address marker is found. If they do not match,
the data is not written to the Receive FIFO and is discarded.
In-Band Bypass-Signaling
In-band bypass-signaling allows a signal to be received at the
local receiver without that signal having to pass through the
Receive FIFO.
When a C0.0 (K28.0) character is received, the RXINT output is
set HIGH. When a C3.0 (K28.3) character is received, the RXINT
output is set LOW. These special codes are generated by forcing
similar transitions into the TXINT input of the CY7C924ADX
HOTLink Transmitter sourcing the data stream.
This output may be used to transport a low data-rate signal (like
a serial RS-232/UART signal) across the interface, without any
significant impact on the actual data being transported across
the link. It may also be used to transparently propagate FIFO
flow-control information across the link by directly connecting the
RXHALF* flag of the local receiver to the TXINT of the local trans-
mitter. The RXINT at the remote end of the link can then be
connected to the TXHALT* input to halt data transfers at the
remote end of the link until the local Receive FIFO has sufficient
room to continue.
8
) possible commands codes. When a
CY7C924ADX
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