AD9858BSVZ Analog Devices Inc, AD9858BSVZ Datasheet - Page 15

• Manufacturer Part Number: AD9858BSVZ
• Description: IC DDS DAC 10BIT 1GSPS 100-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9858BSVZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
• Resolution (bits): 10 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 3.14 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Pll Type: Frequency Synthesis
• Frequency: 1GHz
• Supply Voltage Range: 3.135 To 3.165V, 4.75V To 5.25V
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9858/TLPCBZ - BOARD EVAL TRANSLATION LOOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Charge Pump (CP)
The charge pump output reference current is determined by an
external resistor (~2.4 kΩ), which establishes a 500 μA maximum
internal baseline current (I
provide the appropriate drive current for the various operating
modes (frequency detect, wide closed-loop, and final closed-
loop) of the CP. The amount of scaling in each mode is
programmable by means of the values stored in the control
function register, giving the user maximum flexibility of the
frequency locking capability of the PLL.
The CP polarity can be configured as either positive or negative
with respect to PD
leads PD
the VCO control node. If DIV
to increase the voltage at the VCO control node. When the CP
polarity is negative, the opposite occurs. This allows the user to
define either input as the feedback path. This also allows the
AD9858 to accommodate ground-referenced or supply-referenced
VCOs. This functionality is defined by the charge pump polarity
bit in the control function register, CFR[10].
Internal to the CP, the I
output drive current values for the various modes of operation.
In normal operating mode, the final closed-loop mode can be
programmed to scale I
pump current offset bit, CFR[13], applies a 2 mA offset to the
programmed charge pump current, allowing I
of 5, 6, 7, or 8. The wide closed-loop mode can be programmed
to scale I
mode can be programmed to scale I
different modes of operation, controlled by the fast locking
logic, are discussed in the Fast Locking Logic section.
The CP has an independent set of power pins that can operate
at up to 5.25 V. While the device can operate from ground to
rail, the voltage compliance should be kept in the 0.5 V to
4.5 V range to ensure the best steady-state performance. The
combination of programmable output current, programmable
polarity, wide compliance range, and a proprietary fast lock
capability offers the flexibility necessary for the digital PLL to
operate within a broad range of PLL applications.
Fast Locking Logic
The charge pump includes a fast locking algorithm that helps
to overcome the traditional limitations of PLLs with regard to
frequency switching time. The fast locking algorithm works in
conjunction with the loop filter shown in Figure 29 to provide
extremely fast frequency switching performance.
IN
CP0
, the charge pump attempts to decrease the voltage at
by 0, 2, 4, 6, 8, 10, 12, or 14. The frequency detect
IN
. When the CP polarity is positive, if DIV
CP0
CP0
by 1, 2, 3, or 4. Setting the charge
current is scaled to provide different
CP0
IN
). The baseline current is scaled to
lags PD
CP0
IN
by 0, 20, 40, or 60. The
, the charge pump works
CP0
scaler values
Rev. C | Page 15 of 32
IN
Based on the error seen between the feedback signal and the
reference signal, the fast locking algorithm puts the charge
pump into one of three states: frequency detect mode, a wide
closed-loop mode, or a final closed-loop mode. In the frequency
detect mode, the feedback and reference signals register
substantial phase and frequency errors. Rather than operating
in a continuous closed-loop feedback mode, the charge pump
supplies a fixed current of the correct polarity to the VCO control
node that drives the loop towards frequency lock. When frequency
lock is detected, the fast locking logic shifts the part into one of
the closed-loop modes. In the closed-loop modes, either wide
or final, the charge pump supplies current to the loop filter as
directed by the PFD. The frequency detect mode is intended to
bring the system to a level of frequency lock from which the
intermediary closed-loop system can quickly achieve phase lock.
The level of frequency lock accuracy aimed for is typically
referred to as the lock range. When the frequency is within
the lock range, the time required to achieve phase lock can be
determined by standard PLL transient analysis methods. The
charge pump current sources associated with the frequency
detect mode are connected to Pin 64 (CPFL), and the closed-
loop current sources are connected to Pin 65 (CP) and Pin 66 (CP).
Pin 64 is connected directly to the loop filter zero compensation
capacitor, as shown in Figure 29. This connection allows the
smoothest transition from the frequency detect mode to the
closed-loop modes and enables faster overall switching times.
Pin 65 and Pin 66 are connected to the loop filter in the
conventional manner.
The frequency detection block works as follows. The comparison
logic in the frequency detection circuitry operates one eighth of
the DDS system clock. A comparison is made of the frequencies
present at PD
To ensure that frequency lock detection is achieved while the
frequency difference is within the PLL lock range, the slew rate
of the VCO input should be limited such that the lock range
cannot be traversed within 152 system clock cycles. The slew
rate of the VCO input is determined by the programmed level
of frequency detect current and the size of the zero compensation
capacitor according to the following relationship:
dv
dt
=
I
Figure 29. Charge Pump to Loop Filter Connection
C
IN
f
det
Z
AD9858
and DIV
IN
CPFL
over 19 DDS clock cycles.
CP
CP
R2
C2
AD9858