DP83953VUL National Semiconductor, DP83953VUL Datasheet - Page 61

• Manufacturer Part Number: DP83953VUL
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83953VUL

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 870mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83953VUL

7.0 RIC2A Registers
Upper Event Count Mask Register (Page 0H Address 13H)
The bits in this register effect the Upper and Lower Port Event Count Registers (ECR) on Page (3) addresses 12H to
1FH, and Page (4) addresses 12H to 1DH.
Note: To count all collisions, both the TXCOLC and RXCOLC bits must be set. The OWCC bit should not be set because the port counter will be incremented
twice when an out of collision window collision occurs. The OWCC bit alone should be set if only out of window collisions are to be counted.
Event Record Mask Register (Page 0H Address 14H)
Note: Writing a 1 enables the event to be recorded.
D(7:6)
D0
D1
D2
D3
D4
D5
D6
D7
Bit
Bit
D0
D1
D2
D3
D4
D5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BDLNKE
D7
resv
R
R
D7
BDLNKE
RXCOLC
ELBERE
TXCOLC
Symbol
Symbol
NSFDE
PLERE
PARTE
OWCE
OWCC
JABE
SEE
ROR
FWF
resv
resv
D6
resv
PARTE
D6
(Continued)
Jabber Enable: Enables recording of Jabber Protect events.
Elasticity Buffer Error Enable: Enables recording of Elasticity Buffer Error events.
Phase Lock Error Enable: Enables recording of Carrier Error events.
Non SFD Enable: Enables recording of Non SFD packet events.
Short Event Enable: Enables recording of Short events.
Out of Window Collision Count Enable: Enables recording of Out Of Window
Collision events only.
Partition Enable: Enables recording of Partition events.
Bad Link Enable: Enables recording of Bad Link events.
OWCC
Reset on Read: This bit selects the action a read operation has upon a port's
event counter:
0: No effect upon register contents.
1: The counter register is reset.
Freeze When Full: This bit controls the freezing of the Event Count registers when
the counter is full (FFFF Hex).
Reserved for future use: This bit should be written with a low logic level.
Transmit Collision Count Enable: Enables recording of transmit collision events
only.
Receive Collision Count Enable: Enables recording of receive collision events
only.
Out of Window Collision Count Enable: Enables recording of out of window
collision events only.
Reserved for future use: These bits should be written with a low logic level.
OWCE
D5
D5
RXCOLC
SEE
D4
D4
61
TXCOLC
NSFDE
D3
D3
Description
Description
D2
resv
PLERE
D2
D1
FWF
ELBERE
D1
D0
ROR
JABE
D0
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