DP83953VUL National Semiconductor, DP83953VUL Datasheet - Page 28

• Manufacturer Part Number: DP83953VUL
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83953VUL

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 870mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83953VUL

4.0 Functional Description
Some bus transceivers are of the inverting type. To allow
the Inter-RIC bus to utilize these transceivers, the RIC2A
may be configured to invert the active states of the ACTN,
ANYXN, COLN and IRE signals from active low to active
high. Thus they become active low once more when
passed through an inverting bus driver. This is particularly
important for the ACTN and ANYXN bus lines, since these
signals must be used in a wired-or configuration. Incorrect
signal polarity would make the bus unusable.
4.6 Processor and Display Interface
The processor interface pins, which include the data bus,
address bus and control signals, actually perform three
operations which are multiplexed on these pins. These
operations are:
1. The Mode Load Operation, which performs a power up
2. Display Update Cycles, which are refresh operations for
3. Processor Access Cycles, which allows µP’s to commu-
These three operations are described below.
Mode Load Operation
The Mode Load Operation is a hardware initialization pro-
cedure performed at power on. It loads vital device configu-
ration information into on chip configuration registers. In
addition to its configuration function, the MLOAD pin is the
RIC2A's reset input. When MLOAD is low, all of the
RIC2A's repeater timers, state machines, segment partition
logic and hub management logic are reset.
The Mode Load Operation may be accomplished by attach-
ing the appropriate set of pull up and pull down resistors to
the data and register address pins to assert logic high or
low signals onto these pins, and then providing a rising
edge on the MLOAD pin as is shown in Figure 11. Proper
execution of this function not only requires both falling and
rising edges of MLOAD, but also an active CLKIN through-
out. The mapping of chip functions to the configuration
inputs is shown in Table 1.
In a complex repeater system, the Mode Load Operation
may be performed using a processor write cycle. This
would require the MLOAD pin to be connected to the
CPU's write strobe via some decoding logic, and included
in the processor's memory map.
To support the security options, pin D0 of the data bus dur-
ing MLOAD is assigned to configure RIC2A. A pull up (non-
security mode) or a pull down (security mode) on this pin
defines the desired security level. By using this bit, the user
could also take advantage of the learning mode, as
described below.
Learning of Port Source Address(es)
Learning mode could be invoked in two ways according to
bit D0 of MLoad configuration. Only the port CAMs are
capable of learning the addresses:
1. When D0=0, upon power up and by default, LME, SME,
initialization cycle upon the RIC2A.
updating the display LEDs.
nicate with the RIC2A’s registers.
ESA and EDA bits in the Port Security Configuration
(Continued)
28
2. When D0=1 for MLOAD, security could still be done, but
It is important to note that RIC2A will learn the address of
the packet if LME is set regardless of the D0 setting of
MLoad, i.e. secure or non-secure mode.
It is also very important to note that for proper address
learning, LME and SAC should not be set together.
When the repeater is in non-secure mode, then the com-
parison will not take place between the incoming address
and the learned address.
When the repeater is in secure mode, and the LME bit is
set, then the processor read/write access will be ignored
for the port CAM entries. That is read/ write cycles are
completed, however unknown values are read during the
learning process. Data will not be written into the CAM
entries until the end of the learning process.
It may be desired not to randomize the outgoing data and
transmit the data intact when there is a valid source
address mismatch. The Generate Random Pattern bit,
GRP in the Global Security Register, will provide the
option.
If GRP is set (GRP=1) and there is a source address mis-
match, then RIC2A will not generate random pattern; the
packet will be transmitted out and the Hub Manager will be
informed about the source address mismatch.
For this option to work properly, GRP=ESA=1 and EDA=0.
If EDA is also set to 1, then the packet will be randomized
on ports with valid DA mismatches, and this functionality
will not work.
Register (PSCR) are set globally. This means that each
port will learn the address of the node connected to it by
the reception of the first good packet. The second ad-
dress is learned only if it is different from the first one.
Only the address of a valid length packet without FAE
(Frame Alignment Error) and/or CRC errors can be
learned. As soon as the address is learned by any of the
two CAM locations, RIC2A will set the corresponding
ADV (Address Valid) bit in Port CAM Pointer Register.
To start the address comparison, the SAC (Start Com-
parison) bit must be set (SAC=1) by the user. RIC2A will
only use this CAM location for comparison when the
ADV bit is set (ADV=1), whether LME is 1 or 0. These
four bits in PSCR could be disabled later on a per port
basis, which allow all the packets regardless of their ad-
dress to pass through the repeater.
this time it means that the user should set the LME, SME,
ESA and/or EDA bits in the Port Security Configuration
Register. The rest of the operation is the same as when
D0 is equal to zero.
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