DP83953VUL National Semiconductor, DP83953VUL Datasheet - Page 29

• Manufacturer Part Number: DP83953VUL
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83953VUL

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 870mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83953VUL

4.0 Functional Description
Name
RA0
RA1
RA2
RA3
RA4
Pin
D0
D1
D2
D3
D4
D5
D6
D7
Program-
MIN/MAX
Function
TXONLY
LPPART
SCRTY
DPART
CCLIM
OWCE
EXPLL
ming
BINV
TW2
resv
TP
TP
Minimum Mode Maximum Mode The operation of the display update block is controlled by
Table 1. Pin Definitions for Options in the Mode Load Operation
Not Permitted
External PLL
Effect when
Active High
Selected
Selected
Selected
Selected
Security
Bit is 0
Signals
Mode
5 bits
63
X
X
(Continued)
Active Low Sig-
Non-Security
Effect when
Not Selected
Not Selected
Not Selected
Not Selected
Internal PLL
Required
Bit is 1
Mode
3 bits
nals
31
X
X
29
This bit configures RIC2A security feature options.
When D0 =0 LME, SME, ESA, EDA bits in the Port
Security Configuration Register (PSCR) are set globally.
When D0=1 security can still be done, but now the user
needs to set the above bits in the PSCR register.
This allows the user to select one of two values for the
repeater specification TW2 time. The lower limit (3 bits)
meets the IEEE specification. The upper limit (5 bits) is not
specification compliant but may provide users with higher
network throughput by avoiding spurious network activity
gaps when using coaxial (10BASE2, 10BASE5) network
segments.
The partition specification requires a port to be partitioned
after a certain number of consecutive collisions. The
RIC2A has two values available to allow users to customize
the partitioning algorithm to their environment. Please refer
to the Partition State Machine, in data sheet section 7.3.
The RIC2A may be configured to partition a port if the
segment transceiver does not loopback data to the port
when the port is transmitting to it, as described in the
Partition State Machine.
This configuration bit allows the on-chip partition algorithm
to include out of window collisions into the collisions it
monitors, as described in the Partition State Machine.
This configuration bit allows the on-chip partition algorithm
to restrict segment reconnection, as described in the
Partition State Machine.
The Partition state machines for all ports may be disabled
by writing a logic zero to this bit during the mode load
operation.
the value of this configuration bit, as described in the
Display Update Cycles section.
All ports (2 to 13) use the internal 10BASE-T transceivers.
(Internally configured)
This selection determines whether the Inter-RIC signals:
IRE, ACTN, ANYXN, COLN and Management bus signal
MCRS are active high or low.
If desired, the RIC2A may be used with an external
decoder, this configuration bit performs the selection.
To ensure correct device operation, this bit must be written
with a logic one during the mode load operation.
Function
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