DP83953 National Semiconductor, DP83953 Datasheet
DP83953
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DP83953 Summary of contents
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... Repeater Interface Controller with Security Features, Internal Drivers and Integrated Filters General Description The DP83953 Repeater Interface Controller with Security Features and Integrated Transmit Filters (RIC2A en- hanced version of the DP83952 Repeater Interface Control- ler with Security Features (RIC II). The RIC2A integrates driver and filter circuitry into the RIC II design ...
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... Table of Contents 1.0 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.0 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Summary of DP83953 RIC2A Feature Enhancements from DP83952 RIC 4.2 Overview Of RIC2A Functions . . . . . . . . . . . . . . . 12 4.3 Description Of Repeater Operations . . . . . . . . . . 14 4.4 Examples Of Packet Repetition Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 Description Of Hardware Connection For Inter-ric Bus ...
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... Connection Diagram DataSheet4U.com 4 DataSheet U .com DataSheet4U.com Order Number DP83953VUL NS Package Number VUL160A 3 DataShee www.national.com ...
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Connection Diagram PIN NAME PIN NO. GNDP13 40 TXO13- 39 TXO13+ 38 TXO12- 37 TXO12+ 36 GNDP12 35 V P12 34 DD RXI12- 33 RXI12+ 32 RXI11- 31 RXI11 P11 29 DD GNDP11 28 TXO11- 27 ...
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Pin Descriptions Pin Name Network Interface Pins RXI2- to RXI13- RXI2+ to RXI13+ TXO2- to TXO13- TXO2+ to TXO13+ FILTTL REQ RTX AUI Port CD1+ CD1- RX1+ RX1- TX1+ TX1 Twisted Pair interface compatible ...
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Pin Descriptions Pin Name Processor Bus Pins RA0 - RA4 STR0 STR1 BUFEN RDY ELI DataSheet4U.com 4 DataSheet U .com (Continued) Driver Pin No. I/O Type TT I REGISTER ADDRESS INPUTS: These five pins are ...
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Pin Descriptions RTI CDEC WR RD MLOAD TT = TTL compatible Bi-directional CMOS compatible Open Drain Input Output high impedance DataSheet4U.com 4 DataSheet U .com (Continued) ...
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Pin Descriptions Pin Name Pin No. Inter-RIC Bus Pins ACKI ACKO IRD IRE IRC COLN PKEN CLKIN ACTND ACTNS ANYXND ANYXNS TT = TTL compatible Bi-directional CMOS compatible Open Drain ...
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Pin Descriptions Pin Name Management Bus Pins MRXC MCRS MRXD MEN PCOMP External Decoder Pins RXMPLL Test Pins TEST_(12:7) TEST_(6:2) TEST_1 Power and Ground Pins V 1, 55, 65, 74, 80, 102 DD GND 54, 64, 73, 79, ...
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Block Diagrams DataSheet4U.com 4 DataSheet U .com DataSheet4U.com Figure 1. Shared Repeater and Segment Functional Blocks 10 DataShee www.national.com ...
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Block Diagrams Note: The block diagram for the RIC2A, when used in the non-secure mode, is identical to the “shared” repeater functional block diagram.( Figure 1 ). But, in secure mode, additional security logic is used when operating ...
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... The functionality of the DP83953 is essentially similar to DP83952, but some of the pin definitions have been modified to reflect the new integrated drivers and trans- mit filters. Therefore, the RIC2A is not a drop in replace- ment for the RICII ...
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Functional Description the case of a source address mismatch, the RIC2A will immediately switch to a random bit pattern on both the local transmitting ports and the IRB. The main state machine operates in conjunction with a series ...
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Functional Description The notification of collisions occurring across the network is just as important as data transfers. The Inter-RIC bus has a set of status lines capable of conveying collision information between RIC2As in order to ensure that ...
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Functional Description Repeater Port and Main State Machines The Port and Main State Machines are described with ter- minology used in the IEEE Repeater specification. For a detailed explanation of terms, please refer to that specifica- tion. References ...
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Functional Description DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Figure 4. IEEE Repeater Main State Diagram 16 DataShee www.national.com ...
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Functional Description The Port State Machine (PSM) The two primary functions of the PSM are to: 1. Control the transmission of repeated data, pseudo ran- dom data, and jam signals over the attached segments. 2. Determine if a ...
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Functional Description The IRB connects multiple RIC2As to realize the following operations: Port N Identification (which port the repeater receives data from) Port M Identification (which port last experienced a colli- sion) Data Transfer RECEIVE COLLISION identification Inter-RIC ...
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Functional Description Methods of RIC2A Cascading In order to build multi-RIC2A repeaters, PORT N and PORT M identification must be performed across all the RIC2As in the system. Inside each RIC2A, the PSMs are arranged in a logical ...
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Functional Description Figure 5 shows two RIC2As A and B, daisy chained together with RIC2A-A positioned at the top of the chain packet is received at port B1 of RIC2A-B, and then repeated to the other ...
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Functional Description Note: 1* The activity shown represents the transmitted signal after being looped back by the attached transceiver. DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Figure 6. Data Repetition 21 DataShee ...
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Functional Description Note: 1 SEND PREAMBLE, SEND SFD, SEND DATA AUI port shown. DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Figure 7. Receive Collision 22 DataShee www.national.com ...
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Functional Description Receive Collisions (AUI Port only) A receive collision is a collision which occurs on the net- work segment attached to the AUI port. The collision is "received" similar manner as a data packet is ...
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Functional Description on its segment, but in addition it is higher in the arbitration chain. This priority yields no benefits for port A1 since the ANYXN signal is still active. There are now two sources driving ANYXN, the ...
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Functional Description Note: The Inter-RIC bus is configured to use active low signals. AUI port shown DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Figure 8. Transmit Collision 25 DataShee www.national.com ...
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Functional Description Note: 1* The IEEE Specification does not have a jabber protect state defined in its main state diagram, this behavior is defined in an additional MAU Jabber Lockup Protection state diagram. Note: The Inter-RIC bus is ...
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Functional Description Note Bus Drive Enable active high, /RE = Bus Receive Enable active low Note: The Inter-RIC bus is configured to use active low signals. 4.5 Description Of Hardware Connection For In- ter-ric Bus When ...
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Functional Description Some bus transceivers are of the inverting type. To allow the Inter-RIC bus to utilize these transceivers, the RIC2A may be configured to invert the active states of the ACTN, ANYXN, COLN and IRE signals from ...
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Functional Description Program- Pin ming Name Function D0 SCRTY D1 TW2 D2 CCLIM D3 LPPART D4 OWCE D5 TXONLY D6 DPART D7 MIN/MAX RA0 TP RA1 TP RA2 BINV RA3 EXPLL RA4 resv DataSheet4U.com 4 DataSheet U .com ...
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Functional Description 4.7 Description Of Hardware Connection For Pro- cessor And Display Interface Display Update Cycles The RIC2A possesses control logic and interface pins which may be used to provide status information concern- ing activity on the attached ...
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Functional Description Signal Pin Name D0 Provides status information concerning the Link Integrity status of 10BASE-T segments. This signal should be connected to the data inputs of the chosen pair of 74LS259 latches. D1 Provides status information indicating ...
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Functional Description DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Figure 12. Maximum Mode LED Display (All Available Status Bits Used) 32 DataShee www.national.com ...
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Functional Description DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Figure 13. Processor Connection Diagram 33 DataShee www.national.com ...
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... DataSheet U .com (Continued) Interrupt Handling The DP83953 RIC2A offers an alternative method for a faster access to determine the source of the Event Logging Interrupt (ELI) register than the DP83950 RIC. For an event logging interrupt due to flag found, the DP83950 RIC requires the following scheme: 1 ...
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HUB MANAGEMENT SUPPORT The RIC2A provides information regarding the status of its ports and the packets being repeated. This data is avail- able in three forms: 1. Counted Events - Network events accumulated into the RIC2A's 16 bit ...
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HUB MANAGEMENT SUPPORT The port event counters may also be controlled by the Counter Decrement (CDEC) pin. As the name suggests, a logic low state on this pin will decrement all the counters by a single value. The ...
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HUB MANAGEMENT SUPPORT Short Event reception (SE): This flag goes active if the received packet is less than 74 bits long and no collision occurs during reception. 5.3 Management Interface Operation The Hub Management interface provides a mechanism ...
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HUB MANAGEMENT SUPPORT Thus all of the other status fields can be correctly attrib- uted to the relevant port. 2. The status flags that the RIC2A produces for the event counters or recording latches are supplied with each ...
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HUB MANAGEMENT SUPPORT Packet status Register PSR PSR(0) PSR(1) PSR(2) PSR(3) Collision Bit Timer PSR(4) Lower Repeat Byte Count PSR(5) Upper Repeat Byte Count PSR(6) Inter Frame Gap Bit Timer Note 1: These registers may only be reliably ...
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HUB MANAGEMENT SUPPORT DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Operation of the Management Bus Figure 15. 40 DataShee www.national.com ...
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HUB MANAGEMENT SUPPORT Packet Status Register Bit Symbol D0 resv D1 PCOMPD D(7:2) A(5:0) Packet Status Register 1 D7 CRCER Bit Symbol D(3:0) PA(3:0) D4 CLN D5 COL D6 FAE D7 CRER DataSheet4U.com 4 DataSheet ...
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HUB MANAGEMENT SUPPORT Packet Status Register Bit Symbol D(1:0) CT(9:8) D2 JAB D3 ELBER D4 CRER D5 NSFD D6 OWC D7 SE Modified Packet Status Register 5 (MPS=1 in GSR register) RIC2A provides an option ...
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HUB MANAGEMENT SUPPORT Collision Bit Timer The Collision Timer counts, in bit times, the time between the start of repetition of the packet and the detection of the packet's first collision. When a collision occurs, the Colli- sion ...
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Port Block Functions The RIC2A has 13 port logic blocks (one for each network connection). In addition to the packet repetition operations already described, the port block performs two other func- tions: 1. the physical connection to the ...
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... DataSheet4U.com ules. These modules are currently available from Halo, Bel- fuse, Pulse, and Valor magnetics suppliers. This is a point for reference only. National Semiconductor does not qualify, recommend or claim conformance with any such device. Peak Differential Output Voltage (V Without any resistive loading on the R ...
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Port Block Functions Electrical Specification: OCL (1-3) (6-8), (9-11), (14-16) min. 200 Cww (1-3) to (14-16) (6-8) to (9-11) LL (1,3 & short 14,16) (6,8 & short 9,11) DCR (1-3) (6-8) = (11-9) (14-16) Where C = 0.01 ...
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Port Block Functions RJ45 connecting the resistor to GND will decrease V degree of change is related to the resistor value. The REQ input can be used to adjust the shape of the waveform for all outputs. By ...
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Port Block Functions DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Figure 21. IEEE Segment Partition Algorithm 48 DataShee www.national.com ...
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Port Block Functions 6.4 Local Ports and Expected Activity The RIC2A incorporates security options into the repeater. The configuration of the security features can be performed globally per port basis. Upon packet reception by the ...
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RIC2A Registers RIC2A Register Address Map The RIC2A's registers may be accessed by applying the required address to the five Register Address (RA(4:0)) input pins. Pin RA4 makes the selection between the upper and lower halves of the ...
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RIC2A Registers 19H 1AH 1BH 1CH 1DH 1EH 1FH IFG Threshold Select Address PAGE (4) 11H Port 1 ECR-2 12H Port 2 ECR-2 13H Port 3 ECR-2 14H Port 4 ECR-2 15H Port 5 ECR-2 16H Port 6 ...
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RIC2A Registers Address PAGE (13) 11H SCAM Lo 18 12H CLMR Lo Loc 18 13H CLMR Hi Loc 18 14H SCAM Lo 19 15H CLMR Lo Loc 19 16H CLMR Hi Loc 19 17H SCAM Lo 20 18H ...
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RIC2A Registers Address D7 (Hex BDLNK 1E ER8 1F DLU Address D7 (Hex even EC7 locations odd EC15 locations Address D7 (Hex EC7 1E res 1F ADV Address D7 (Hex) ...
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RIC2A Registers Address D7 (Hex) 11 ADV 12, 13 PCAMx_D7 14 res 15 ADV 16, 17 PCAMx_D7 18 res 19 ADV 1A, 1B PCAMx_D7 1C res 1D ADV 1E, 1F PCAMx_D7 Address D7 (Hex) 11 res 12 ADV ...
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RIC2A Registers Address D7 (Hex) 11 PCAMx _D7 12 res 13 ADV 14, 15 PCAMx _D7 16 ADV8 17 ADV16 18 ADV24 19 ADV32 1A SCAMx _D7 PTR2 1D SCAMx _D7 PTR2 ...
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RIC2A Registers RIC2A Status and Configuration Register (Address 00H) The lower portion of this register contains real time information concerning the operation of the RIC2A. The D7 bit repre- sent the chosen configuration of the transceiver interface employed. ...
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... Squelch Levels 0: Port operates with normal IEEE receive squelch level. 1: Port operates with reduced receive squelch level. Note 1: In addition to hysteresis that DP83950 RIC provides on normal receive squelch, DP83953 RIC2A provides a hysteresis when operating in the reduced squelch level mode. DISPT Disable Port 0: Port operates as defined by repeater operations ...
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RIC2A Registers RIC2A Configuration Register This register displays the state of a number of RIC2A configuration bits loaded during the Mode Load operation. D7 MINMAX Bit R ...
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RIC2A Registers Real Time Interrupt Register (Address 0FH) The Real Time Interrupt register (RTI) contains information which may change on a packet by packet basis. Any remain- ing interrupts which have not been serviced before the following packet ...
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... Device Type Register (Page 0H Address 11H) This register may be used to distinguish different revisions of RIC. It will return the value 91 H for the DP83953 RIC2A device. It will return the value 8X operations to this register have no effect upon the contents Lower Event Count Mask Register (Page 0H Address 12H) ...
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RIC2A Registers Upper Event Count Mask Register (Page 0H Address 13H) The bits in this register effect the Upper and Lower Port Event Count Registers (ECR) on Page (3) addresses 12H to 1FH, and Page (4) addresses 12H ...
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RIC2A Registers Event Count and Interrupt Mask Register 2 (ECIMR-2) (Page 0H Address 15H) The bits in this register effect the Port Event Count Register 2, PECR-2 on Page 4, Addresses 11H to 1DH. D7 res Bit R/W ...
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RIC2A Registers Interrupt and Management Configuration Register (Page 0H Address 16H) This register powers up with all bits set to one and must be initialized by a processor write cycle before any events will generate interrupts. D7 IFC ...
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RIC2A Registers Packet Compress Decode Register (Page 0H Address 18H) This register is used to determine the number of bytes in the data field of a packet which are transferred over the manage- ment bus when the packet ...
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RIC2A Registers Inter Frame Gap Threshold Select Register (Page 0H Address 1FH) This register is used to configure the hub management interface to provide a certain minimum inter frame gap between packets transmitted over the management bus. The ...
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RIC2A Registers Lower Event Information Register (Lower EIR) (Page 1H Address 1FH) D7 DLU Bit R ER9 D1 R ER10 D2 R ER11 D3 R ER12 D4 R ER13 D5 R resv D6 R resv D7 ...
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RIC2A Registers Port Event Count Register 2 (PECR-2) (Page 4H Addresses 11H to 1DH) The Port Event Count Register 2 (PECR-2) shows the instantaneous value of the specified port bit counter. The counter increments when an ...
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RIC2A Registers Port CAM Pointer Register (PCPR) (Pages 4H, 5H, 6H, 8H, 9H) This register indicates which bytes of the six ethernet address bytes has been stored in the CAM locations. When a byte has been loaded into ...
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RIC2A Registers Shared CAM Validation Register 1 (SCVR 1) (Page 9H Address 16H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs. When a “1” is written in a specific ...
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RIC2A Registers Shared CAM Validation Register 2 (SCVR 2) (Page 9H, Address 17H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs. When a “1” is written in a specific ...
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RIC2A Registers Shared CAM Validation Register 3 (SCVR 3) (Page 9H, Address 18H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs. When a “1” is written in a specific ...
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RIC2A Registers Shared CAM Validation Register 4 (SCVR 4) (Page 9H Address 19H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs. When a “1” is written in a specific ...
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RIC2A Registers Shared CAM Register (Pages 9H, AH, BH, CH, DH, EH, FH) This register accesses the 48 bits of the shared CAM address. Six write/read cycles are required to load/read the entire 48 bit address. D7 SCAMx_D7 ...
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RIC2A Registers CAM Location Mask Register (CLMR) (Pages 9H, AH, BH, CH, DH, EH, FH) Each shared CAM has a CLMR, therefore there are 32 CLMRs. Any of the 32 CAMs can be shared among the ports. For ...
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Board Layout Recommendations There are numerous methods to layout PCB boards to achieve successful proper operation. Two options for the RIC2A layout are presented here. These NSC recommen- dations have not been empirically proven in the laboratory. Power ...
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Figure 24. The RIC2A Ground Plane is Divided into 3 Regions to Minimize Noise Effects Figure 25. The RIC2A Metal Layer Configuration used to Sink Additional Current DataSheet4U.com 4 DataSheet U .com Figure 26. Configuration for Decoupling Capacitors across ...
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DC and AC Specification Absolute Maximum Ratings Supply Voltage ( ) Input Voltage ( Output Voltage (V out ) Storage Temperature Range (T STG ) Power Dissipation for chip (P Lead Temp. ...
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DC and AC Specification AC Specifications Port Arbitration Timing Number Symbol T1 ackilackol T2 ackihackoh Note 1: Timing valid with no receive or collision activities. Note 2: In these diagrams the Inter-RIC and Management Busses are shown using ...
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DC and AC Specification Receive Timing-10Base-T Ports Receive activity propagation start up and end delays for 10BASE-T ports Number Symbol T3t rxaackol T4t rxiackoh T5t rxaactna T6t rxiactni ACKI Note: assumed high Transmit Timing-AUI Ports Transmit activity propagation ...
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DC and AC Specification Transmit Timing-10Base-T Ports Receive activity propagation start up and end delays for 10BASE-T ports Number Symbol T15t actnatxa ACKI Note: assumed high COLLISION TIMING - AUI PORT Collision activity propagation start up and end ...
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DC and AC Specification Receive Collision Timing Number Symbol T32a cdacolna T33a cdicolni T39 colnajs T40 colnije Note 1: PKEN assumed high Note 2: Assuming reception ended before COLN goes inactive. TW2 is included in this parameter. Assuming ...
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DC and AC Specification Collision Timing-AUI Port Number Symbol T34 anyamin T35 anyitxai T38 anyasj Number Symbol T36 actnitxi T37 anyitxoi DataSheet4U.com 4 DataSheet U .com (Continued) Parameter ANYXN active time ANYXN inactive all inactive ...
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DC and AC Specification Inter RIC Bus Output Timing Number Symbol T101 ircoh T102 ircol T103 ircoc T104 actndapkena T105 actndairea T106 ireairca T107 irdov T108 irdos T109 ircohirei T110 ircclks DataSheet4U.com 4 DataSheet U .com (Continued) Parameter ...
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DC and AC Specification Inter RIC Bus Input Timing Number Symbol T111 ircih T122 ircil T114 irdisirc T115 irdihirc T116 ircihirei DataSheet4U.com 4 DataSheet U .com (Continued) Parameter IRC input high time IRC input low time IRD input ...
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DC and AC Specification Management Bus Timing Number Symbol T50 mrxch T51 mrxcl T52 mrxcd T53 actndamena T54 actndamcrsa T55 mrxds T56 mrxdh T57 mrxclmcrsi T58 mcrsimenl T59 mrxcclks T60 pcompw Note: The preamble on this bus consists ...
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DC and AC Specification MLOAD TIMING Number Symbol T61 mldats T62 mldath T63 mlabufa T64 mlibufi T65 mlw T65a clkinm Note: Both edges of MLOAD have to be valid for proper setup timing STROBE TIMING Number Symbol T66 ...
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DC and AC Specification CDEC TIMING Number Symbol T70 cdecpw T71 cdeccdec REGISTER READ TIMING Number Symbol T80 rdadrs T81 rdadrh T82 rdabufa T83 rdibufi T84 rdadatv T85 rddath T86 rdardya T87 rdirdyi T88 rdw Note: Minimum high ...
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DC and AC Specification REGISTER WRITE TIMING Number Symbol T90 T91 wradrh T92 wrabufa T93 wribufi T94 wradatv T95 wrdath T96 wrardya T97 wrirdyi T98 wrw T99 wradt Note 1: Assuming zero propagation delay on external buffer. Note ...
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DC and AC Specification AC Timing Test Conditions All specifications are valid only if the mandatory isolation is employed and all differential signals are taken AUI side of the transformer. Input Pulse Levels (TTL/CMOS) Input ...
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... DataSheet4U.com Molded Plastic Quad Package, JEDEC Order Number DP83953VUL NS Package Number VUL160A 2. A critical component is any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system affect its safety or effectiveness ...