DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 63

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER
(Address = A4 to A7 Hex)
16.
The Receive Channel blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel
Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK and TCHBLK pins respectively.
(The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low
during individual channels). These outputs can be used to block clocks to a USART or LAPD controller
in ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK and TCHBLK pin
will be held high during the entire corresponding channel time. See the timing in Section 22 for an
example. The TCBRs have alternate mode of use. By the CCR3.6 bit, the user has the option to use the
TCBRs to determine on a channel by channel basis, which signaling bits are to be inserted by the TSRs
(the corresponding bit in the TCBRs = 1) and which are to be sourced from the TSER or TSIG pins (the
corresponding bit in the TCBR = 0). See the timing in Section 22 for an example.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING REGISTERS
(Address = 2B to 2E Hex)
(MSB)
(MSB)
CH16
CH24
CH32
CH16
CH24
CH32
CH8
CH8
SYMBOL
SYMBOL
CH1–32
CH1–32
CLOCK BLOCKING REGISTERS
CH15
CH23
CH31
CH15
CH23
CH31
CH7
CH7
RCBR1.0–4.7
RCC1.0–4.7
POSITION
POSITION
CH14
CH22
CH30
CH14
CH22
CH30
CH6
CH6
CH13
CH21
CH29
CH5
CH13
CH21
CH29
CH5
Receive Code Insertion Control Bits
0 = do not insert data from the RC register into the receive data
stream
1 = insert data from the RC register into the receive data
stream
Receive Channel Blocking Control Bits
0 = force the RCHBLK pin to remain low during this channel
time
1 = force the RCHBLK pin high during this channel time
CH12
CH20
CH28
CH4
CH12
CH20
CH28
CH4
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NAME AND DESCRIPTION
NAME AND DESCRIPTION
CH11
CH19
CH27
CH3
CH11
CH19
CH27
CH3
CH18
CH10
CH26
CH2
CH10
CH18
CH26
CH2
(LSB)
CH17
CH25
CH1
CH9
(LSB)
CH17
CH25
CH1
CH9
RCBR1 (2B)
RCBR2 (2C)
RCBR3 (2D)
RCBR4 (2E)
RCC1 (A4)
RCC2 (A5)
RCC3 (A6)
RCC4 (A7)