DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 16

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4. DS21FT44 (Four x Three) PCB Land Pattern
The diagram shown below is the pin pattern that is placed on the target PCB. This is the same pattern that
would be seen as viewed through the MCM from the top.
Figure 4-1. PIN PATTERN FOR TARGET PCB (4 X 3)
W
G
M
A
B
C
D
E
H
K
N
P
R
U
V
Y
F
J
L
T
rsync
rsync
tneg
tneg
sync
rpos
rpos
rpos
tpos
rser
tclk
tser
tsig
rclk
rser
tclk
tser
rclk
1
rch
blk
rch
blk
ts
1
1
1
1
2
2
2
2
2
2
5
5
5
5
5
6
6
6
6
6
tsync
rsync
dvdd
sync
dvdd
rneg
rneg
tpos
tpos
rneg
tneg
rpos
rclk
sys
rsig
tclk
rsig
sys
tsig
2
rch
blk
clk
clk
ts
1
1
1
1
2
2
2
2
2
8
5
5
5
2
5
6
6
6
6
6
sync1
rsync
tsync
dvdd
tpos
tneg
rneg
tpos
dvss
rneg
rsig
tser
rser
rclk
tsig
rclk
tser
rch
blk
sys
tclk
3
clk
ts
1
1
1
1
3
2
2
8
2
5
5
5
8
8
8
2
6
8
6
rsync
tsync
dvdd
tsync
rpos
dvss
sync
rpos
sync
dvss
cs2*
tser
tsig
rsig
tsig
rser
rsig
rser
sys
sys
4
clk
clk
ts
ts
4
1
1
3
1
2
3
3
8
2
5
5
8
8
8
9
3
6
6
tsync
tsync
rsync
tsync
dvss
tneg
sync
tpos
tneg
rpos
rsig
tser
tclk
sys
tclk
sys
tclk
rch
tsig
sys
5
clk
clk
blk
clk
ts
4
1
3
1
3
3
3
2
3
8
5
8
8
8
8
7
7
7
6
7
rsync
dvss
clksi
rser
rsig
tser
rch
tclk
rch
rclk
6
blk
blk
1
3
3
3
7
7
7
7
7
rsync
tsync
mclk
dvdd
dvdd
sync
rneg
tpos
tser
rser
7
ts
4
8
1
4
3
7
2
7
7
7
rch
blk
rser4
rsig4
sync
dvss
sync
cs1*
tneg
sys
8
clk
rch
blk
10
ts
ts
4
4
4
2
7
9
rneg
rpos
rneg
dvss
rneg
rclk
rclk
tsig
tser
sys
9
clk
10
10
4
4
4
3
1
9
9
7
16 of 117
10
tneg
tpos
rpos
tpos
tsig
rclk
rsig
tsig
rclk
jtdi
10
10
10
4
4
4
3
9
9
11
rsync
rpos
rneg
rser
rsig
nc
nc
nc
nc
nc
10
10
10
9
9
12
dvdd
tneg
rser
sys
rch
clk
11
10
blk
10
10
nc
nc
nc
nc
nc
3
13
tsync
rsync
tsync
test
tclk
tclk
nc
nc
nc
nc
10
10
10
9
9
14
tpos
tneg
jtclk
fs1
fs0
ns
nc
nc
nc
nc
9
9
15
rsync
sync
cs3*
tsig
bts
ns
nc
ns
nc
nc
11
ts
9
9
16
dvdd
tsync
tsync
jtms
dvss
tser
rser
rser
tser
int*
tclk
wr*
nc
nc
nc
nc
nc
nc
nc
nc
12
12
12
11
11
11
3
9
3
17
jtrst*
mux
jtdot
rneg
sync
rclk
sys
rch
rch
A6
A7
D6
D7
12
clk
12
blk
12
blk
11
11
11
nc
nc
nc
nc
nc
nc
nc
ts
18
rsync
tpos
tneg
tsig
tclk
tsig
rclk
rd*
A4
A5
D4
D5
12
12
11
11
11
11
11
nc
nc
nc
nc
nc
nc
nc
nc
tssync
19
dvdd
rpos
tneg
rpos
rsig
A2
A3
D2
D3
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
12
12
12
11
11
3
20
dvss
rneg
tpos
rsig
tser
A0
A1
D0
D1
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
12
12
12
12
3