DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 57

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address = 30 to 3F Hex)
Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two timeslots. The
bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the
Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The user has a full 2ms to retrieve the signaling bits before the data is lost. The RS
registers are updated under all conditions. Their validity should be qualified by checking for
synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract
signaling information. By the SR2.7 bit, the user will be informed when the signaling registers have been
loaded with data. The user has 2ms to retrieve the data before it is lost. The signaling data reported in
RS1 to RS16 is also available at the RSIG and RSER pins.
Three status bits in Status Register 1 (SR1) monitor the contents of registers RS1 through RS16. Status
monitored includes all zeros detection, all ones detection and a change in register contents. The Receive
Signaling All Zeros status bit (SR1.5) is set when over a full multiframe, RS1 through RS16 contain all
zeros. The Receive Signaling All Ones status bit (SR1.7) is set when over a full multiframe, RS1 through
RS16 contain less than three zeros. A change in the contents of RS1 through RS16 from one multiframe
to the next will cause RSA1 (SR1.7) and RSA0 (SR1.5) status bits to be set at the same time.
The user can enable the INT* pin to toggle low upon detection of a change in signaling by setting either
the IMR1.7 or IMR1.5 bit. Once a signaling change has been detected, the user has at least 1.75ms to read
the data out of the RS1 to RS16 registers before the data will be lost.
(MSB)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
SYMBOL
0
D(30)
A(1)
X
Y
B(10)
B(11)
B(12)
B(13)
B(14)
B(15)
B(1)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
0
POSITION
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
RS1.0/1/3
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
RS16.0
0
RS1.2
RS2.7
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9)
0
Spare Bits
Remote Alarm Bit (integrated and reported in SR1.6)
Signaling Bit A for Channel 1
Signaling Bit D for Channel 30
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
A(22)
A(23)
A(24)
A(25)
A(26)
A(27)
A(28)
A(29)
A(30)
X
57 of 117
NAME AND DESCRIPTION
B(16)
B(17)
B(18)
B(19)
B(20)
B(21)
B(22)
B(23)
B(24)
B(25)
B(26)
B(27)
B(28)
B(29)
B(30)
Y
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
C(22)
C(23)
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
X
(LSB)
D(16)
D(17)
D(18)
D(19)
D(20)
D(21)
D(22)
D(23)
D(24)
D(25)
D(26)
D(27)
D(28)
D(29)
D(30)
X
RS1 (30)
RS2 (31)
RS3 (32)
RS3 (33)
RS5 (34)
RS6 (35)
RS7 (36)
RS8 (37)
RS9 (38)
RS10 (39)
RS11 (3A)
RS12 (3B)
RS13 (3C)
RS14 (3D)
RS15 (3E)
RS16 (3F)