DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 34

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 10–1. SYNC/RESYNC CRITERIA
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)
MULTIFRAME
(MSB)
FRAME OR
Sa8S
SYMBOL
LEVEL
CRC4
RBCS
RESE
CAS
FAS
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
—
Sa7S
FAS present in frame N
and N + 2, and FAS not
present in frame N + 1
Two valid MF alignment
words found within 8 ms
Valid MF alignment word
found and previous
timeslot 16 contains code
other than all zeros
POSITION
SYNC CRITERIA
RCR2.7
RCR2.6
RCR2.5
RCR2.4
RCR2.3
RCR2.2
RCR2.1
RCR2.0
Sa6S
Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit
position; set to zero to force RLCLK low during Sa8 bit
position. See Section 22 for timing details.
Sa7 Bit Select. Set to one to have RLCLK pulse at the Sa7 bit
position; set to zero to force RLCLK low during Sa7 bit
position. See Section 22 for timing details.
Sa6 Bit Select. Set to one to have RLCLK pulse at the Sa6 bit
position; set to zero to force RLCLK low during Sa6 bit
position. See Section 22 for timing details.
Sa5 Bit Select. Set to one to have RLCLK pulse at the Sa5 bit
position; set to zero to force RLCLK low during Sa5 bit
position. See Section 22 for timing details.
Sa4 Bit Select. Set to one to have RLCLK pulse at the Sa4 bit
position; set to zero to force RLCLK low during Sa4 bit
position. See Section 22 for timing details.
Receive Side Backplane Clock Select
0 = if RSYSCLK is 1.544MHz
1 = if RSYSCLK is 2.048MHz
Receive Side Elastic Store Enable
0 = elastic store is bypassed
1 = elastic store is enabled
Not Assigned. Should be set to zero when written.
Sa5S
34 of 117
Three consecutive incorrect FAS
received
Alternate (RCR1.2 = 1) the above
criteria is met or three
consecutive incorrect bit 2 of
non-FAS received
915 or more CRC4 code words
out of 1000 received in error
Two consecutive MF alignment
words received in error
RESYNC CRITERIA
Sa4S
NAME AND DESCRIPTION
RBCS
RESE
4.2 and 4.3.2
ITU SPEC.
G.732 5.2
G.706
G.706
4.1.1
4.1.2
(LSB)
—