ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 89
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ISP1362EE
Manufacturer Part Number
ISP1362EE
Description
IC USB CTRL SNGL CHIP 64TFBGA
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1362EEUM.pdf
(153 pages)
Specifications of ISP1362EE
Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1362EE/01
Manufacturer:
KAWASAKI
Quantity:
1 200
Part Number:
ISP1362EE/01
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Company:
Part Number:
ISP1362EEUM
Manufacturer:
IDT
Quantity:
300
NXP Semiconductors
Table 63.
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcHardwareConfiguration register: bit allocation
14.4.1 HcHardwareConfiguration register (R/W: 20h/A0h)
Suspend_
OneDMA
Wakeup
14.4 HC DMA and interrupt control registers
Disable
R/W
R/W
15
0
7
0
Table 62.
The bit allocation of the HcHardwareConfiguration register is given in
Code (Hex): 20 — read
Code (Hex): A0 — write
Bit
1
0
DACKInput
Polarity
Global
Power
Down
R/W
R/W
14
0
6
0
HcRhPortStatus[1:2] register: bit description
Symbol
PES
CCS
PullDown
Connect
Polarity
Output
DREQ
_DS2
R/W
R/W
13
0
5
1
Rev. 05 — 8 May 2007
Description
On read PortEnableStatus: This bit indicates whether the port is
enabled or disabled. The root hub may clear this bit when an
overcurrent condition, disconnect event, switched-off power or
operational bus error, such as babble, is detected. This change also
causes PortEnableStatusChange to be set. The HCD sets this bit by
writing SetPortEnable and clears it by writing ClearPortEnable. This bit
cannot be set when CurrentConnectStatus (CCS) is cleared. This bit
is also set, if it is not already, at the completion of a port reset when
PortResetStatusChange is set or port suspend when
PortSuspendStatusChange is set.
0 — port is disabled
1 — port is enabled
On write SetPortEnable: The HCD sets PortEnableStatus (PES) by
writing logic 1. Writing logic 0 has no effect. If CurrentConnectStatus
(CCS) is cleared, this write does not set PortEnableStatus (PES), but
instead sets ConnectStatusChange (CSC). This informs the driver that
it attempted to enable a disconnected port.
On read CurrentConnectStatus: This bit reflects the current state of
the downstream port.
0 — no device connected
1 — device connected
On write ClearPortEnable: The HCD writes logic 1 to this bit to clear
the PortEnableStatus (PES) bit. Writing logic 0 has no effect.
CurrentConnectStatus (CSC) is not affected by any write.
Remark: This bit always reads logic 1 when the attached device is
nonremovable (DeviceRemovable[NDP]).
PullDown
Connect
_DS1
DataBusWidth[1:0]
R/W
R/W
12
0
4
0
ClkNotStop
Suspend
R/W
R/W
11
0
3
1
AnalogOC
Interrupt
…continued
Polarity
Single-chip USB OTG Controller
Enable
Output
R/W
R/W
10
0
2
0
PinTrigger
Interrupt
OneINT
R/W
R/W
Table
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1362
63.
InterruptPin
Enable
DACK
Mode
R/W
R/W
88 of 152
8
0
0
0