ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 66
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ISP1362EE
Manufacturer Part Number
ISP1362EE
Description
IC USB CTRL SNGL CHIP 64TFBGA
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1362EEUM.pdf
(153 pages)
Specifications of ISP1362EE
Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1362EE/01
Manufacturer:
KAWASAKI
Quantity:
1 200
Part Number:
ISP1362EE/01
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Company:
Part Number:
ISP1362EEUM
Manufacturer:
IDT
Quantity:
300
NXP Semiconductors
Table 28.
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
OtgInterruptEnable register: bit allocation
RESUME_
13.4 OtgInterruptEnable register (R/W: 69h/E9h)
OTG_
R/W
15
IE
7
0
-
-
Table 27.
Code (Hex): 69 — read
Code (Hex): E9 — write
Table 29.
Bit
2
1
0
Bit
15 to 11 -
10
9
8
7
SUSPND_
OTG_
R/W
14
IE
6
0
-
-
Symbol
OTG_TMR_IE
B_SE0_SRP_IE
A_SRP_DET_IE
OTG_RESUME_IE Logic 1 enables interrupt on detecting bus resume (J to K only)
OtgInterrupt register: bit description
OtgInterruptEnable register: bit description
Symbol
B_SESS_
END_C
A_VBUS_
VLD_C
ID_REG_C
CONN_IE
reserved
RMT_
R/W
13
5
0
-
-
Rev. 05 — 8 May 2007
Description
This bit is set whenever the B_SESS_END bit of the OtgStatus
register changes. Write logic 1 to clear this bit. Writing logic 0 has no
effect.
0 — no event
1 — bit B_SESS_END has changed
This bit is set whenever the A_VBUS_VLD bit of the OtgStatus register
changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no event
1 — bit A_VBUS_VLD has changed
This bit is set whenever the ID_REG bit of the OtgStatus register
changes. This is an indication that the mini-A plug is inserted or
removed (that is, the ID pin is shorted to ground or pulled HIGH). Write
logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no event
1 — ID_REG bit has changed
Description
reserved
Logic 1 enables interrupt when the OTG timer attains time-out.
Logic 0 disables interrupt.
Logic 1 enables interrupt on detecting the B_SE0_SRP status
change. Logic 0 disables interrupt.
Logic 1 enables interrupt on detecting the SRP event. Logic 0
disables interrupt.
event. Logic 0 disables interrupt.
B_SESS_
VLD_IE
R/W
12
4
0
-
-
A_SESS_
VLD_IE
R/W
11
3
0
-
-
…continued
B_SESS_
TMR_IE
END_IE
Single-chip USB OTG Controller
OTG_
R/W
R/W
10
0
2
0
A_VBUS_
B_SE0_
SRP_IE
VLD_IE
R/W
R/W
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1362
ID_REG_
A_SRP_
DET_IE
R/W
R/W
65 of 152
IE
8
0
0
0