ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 52
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ISP1362EE
Manufacturer Part Number
ISP1362EE
Description
IC USB CTRL SNGL CHIP 64TFBGA
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1362EEUM.pdf
(153 pages)
Specifications of ISP1362EE
Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1362EE/01
Manufacturer:
KAWASAKI
Quantity:
1 200
Part Number:
ISP1362EE/01
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Company:
Part Number:
ISP1362EEUM
Manufacturer:
IDT
Quantity:
300
NXP Semiconductors
ISP1362_5
Product data sheet
12.2.1 DMA for an IN endpoint (internal Peripheral Controller to the external USB
12.2.2 DMA for OUT endpoint (external USB host to internal Peripheral Controller)
12.2 Device DMA transfer
host)
When the internal DMA handler is enabled and at least one buffer (ping or pong) is free,
the DREQ2 line is asserted. The external DMA controller then starts negotiating for
control of the bus. As soon as it has access, it asserts the DACK2 line and starts writing
data. The burst length is programmable. When the number of bytes equal to the burst
length has been written, the DREQ2 line is de-asserted. As a result, the DMA controller
de-asserts the DACK2 line and releases the bus. At that moment, the whole cycle restarts
for the next burst.
When the buffer is full, the DREQ2 line is de-asserted and the buffer is validated (which
means that it is sent to the host at the next IN token). When the DMA transfer is
terminated, the buffer is also validated (even if it is not full). A DMA transfer is terminated
when any of the following conditions is met:
Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1,
Peripheral Controller DMA controller handshake signals DREQ2 and DACK2 are routed to
DREQ1 and DACK1.
When the internal DMA handler is enabled and at least one buffer is full, the DREQ2 line
is asserted. The external DMA controller then starts negotiating for control of the bus, and
as soon as it has access, it asserts the DACK2 line and starts reading data. The burst
length is programmable. When the number of bytes equal to the burst length has been
read, the DREQ2 line is de-asserted. As a result, the DMA controller de-asserts the
DACK2 line and releases the bus. At that moment, the whole cycle restarts for the next
burst. When all the data is read, the DREQ2 line is de-asserted and the buffer is cleared
(this means that it can be overwritten when a new packet arrives). A DMA transfer is
terminated when any of the following conditions are met:
Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1,
Peripheral Controller DMA controller handshake signals DREQ2 and DACK2 are routed to
DREQ1 and DACK1.
When the DMA transfer is terminated, the buffer is also cleared (even if data is not
completely read) and the DMA handler is automatically disabled. For the next DMA
transfer, the DMA controller as well as the DMA handler must be re-enabled.
•
•
•
•
The DMA count is complete.
DMAEN = 0.
The DMA count is complete.
DMAEN = 0.
Rev. 05 — 8 May 2007
Single-chip USB OTG Controller
© NXP B.V. 2007. All rights reserved.
ISP1362
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