ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 60
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ISP1362EE
Manufacturer Part Number
ISP1362EE
Description
IC USB CTRL SNGL CHIP 64TFBGA
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1362EEUM.pdf
(153 pages)
Specifications of ISP1362EE
Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1362EE/01
Manufacturer:
KAWASAKI
Quantity:
1 200
Part Number:
ISP1362EE/01
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Company:
Part Number:
ISP1362EEUM
Manufacturer:
IDT
Quantity:
300
NXP Semiconductors
ISP1362_5
Product data sheet
Fig 27. Suspend and resume timing
D_SUSPEND/D_WAKEUP
GOSUSP (bit)
12.5.2 Resume conditions
USB bus
INT2
CS
The Peripheral Controller in the ISP1362 will remain in the suspend state for at least 5 ms,
before responding to external wake-up events, such as global resume, bus traffic, CS
active or LOW pulse on the D_SUSPEND/D_WAKEUP pin.
Figure 27
resume operations.
In
A — indicates the point at which the USB bus goes to the idle state.
B — after detecting the suspend interrupt, set and clear the GOSUSP bit in the Mode
register.
C — indicates resume condition, which can be a resume signal from the host, a LOW
pulse on the D_SUSPEND/D_WAKEUP pin, or a LOW pulse on the CS pin.
D — indicates remote wake-up. The ISP1362 will drive a K-state on the USB bus for
10 ms after the D_SUSPEND/D_WAKEUP pin goes LOW or the CS pin goes LOW.
Wake-up from the suspend state is initiated either by the USB host or by the application:
The steps of a wake-up sequence are as follows:
•
•
Figure
USB host: drives a K-state on the USB bus (global resume).
Application: remote wake-up using a LOW pulse on pin D_SUSPEND/D_WAKEUP or
a LOW pulse on pin CS (if enabled using bit WKUPCS of the
DcHardwareConfiguration register).
27:
A
shows a typical timing diagram for the Peripheral Controller suspend and
> 3 ms
suspend
interrupt
Rev. 05 — 8 May 2007
idle state
> 5 ms
B
1.8 ms to
2.2 ms
C
0.5 ms to 3.5 ms
interrupt
resume
Single-chip USB OTG Controller
D
10 ms
K-state
© NXP B.V. 2007. All rights reserved.
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