CY7C68034-56LFXC Cypress Semiconductor Corp, CY7C68034-56LFXC Datasheet - Page 9

• Manufacturer Part Number: CY7C68034-56LFXC
• Description: IC USB NX2LP NAND CNTRLR 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68034-56LFXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• No. Of I/o's: 12
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Digital Ic Case Style: QFN
• Supply Voltage Range: 3V To 3.6V
• Core Size: 8 Bit
• Program Memory Size: 15KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 001-04247 Rev. *D
Endpoint RAM
Size
Organization
For high-speed endpoint configuration options, see Figure 8.
Default Full-Speed Alternate Settings
Table 6. Default Full-Speed Alternate Settings
Notes
ep0
ep1out
ep1in
ep2
2. ‘0’ means ‘not implemented.’
3. ‘2×’ means ‘double buffered.’
• 3 × 64 bytes
• 8 × 512 bytes (Endpoints 2, 4, 6, 8)
• EP0
• EP1IN, EP1OUT
• EP2,4,6,8
— Bidirectional endpoint zero, 64-byte buffer
— 64-byte buffers, bulk or interrupt
— Eight 512-byte buffers, bulk, interrupt, or isochronous.
— EP4 and EP8 can be double buffered, while EP2 and 6
can be either double, triple, or quad buffered.
Alternate Setting
EP0 IN&OUT
EP1 OUT
EP1 IN
(Endpoints 0 and 1)
EP2
EP4
EP8
EP6
512
512
512
512
512
512
512
512
64
64
64
1
EP4
EP6
EP2
512
512
512
512
512
512
512
512
64
64
64
2
64
0
0
0
0
EP2
EP4
EP6
1024
1024
512
512
512
512
64
64
64
3
64
64 bulk
64 bulk
64 bulk out (2×)
Figure 8. Endpoint Configuration
EP2
EP6
EP8
[2, 3]
512
512
512
512
512
512
512
512
64
64
64
4
1
EP2
EP6
512
512
512
512
512
512
512
512
64
64
64
5
EP2
EP6
1024
1024
512
512
512
512
64
64
64
6
Setup Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup
data from a CONTROL transfer.
Endpoint Configurations (High-speed Mode)
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT. The endpoint buffers can be
configured in any 1 of the 12 configurations shown in the
vertical columns. When operating in full-speed BULK mode,
only the first 64 bytes of each buffer are used. For example, in
high-speed the max packet size is 512 bytes, but in full-speed
it is 64 bytes. Even though a buffer is configured to be a 512
byte buffer, in full-speed only the first 64 bytes are used. The
unused endpoint buffer space is not available for other opera-
tions. An example endpoint configuration would be:
EP2–1024
(column 8 in Figure 8).
64
64 int
64 int
64 int out (2×)
EP2
EP8
EP6
1024
1024
512
512
512
64
64
64
512
7
double
EP2
1024
1024
EP6
512
512
512
512
64
64
64
8
2
CY7C68033/CY7C68034
EP2
EP6
1024
1024
1024
1024
buffered;
64
64
64
9
EP2
EP6
EP8
512
512
512
512
512
512
512
512
64
64
64
10
64
64 int
64 int
64 iso out (2×)
EP6–512
EP8
EP2 EP2
1024
1024
1024
1024
64
64
64
512
512
11
1024
1024
1024
1024
12
64
64
64
quad
3
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