CY7C68034-56LFXC Cypress Semiconductor Corp, CY7C68034-56LFXC Datasheet - Page 12

• Manufacturer Part Number: CY7C68034-56LFXC
• Description: IC USB NX2LP NAND CNTRLR 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68034-56LFXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• No. Of I/o's: 12
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Digital Ic Case Style: QFN
• Supply Voltage Range: 3V To 3.6V
• Core Size: 8 Bit
• Program Memory Size: 15KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 001-04247 Rev. *D
Pin Assignments
Figure 9 and Figure 10 identify all signals for the 56-pin
NX2LP-Flex package.
Three modes of operation are available for the NX2LP-Flex:
Port mode, GPIF Master mode, and Slave FIFO mode. These
modes define the signals on the right edge of each column in
Figure 9. The right-most column details the signal functionality
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDATA
DPLUS
DMINUS
Port
INTO#/PA0
INT1#/PA1
WU2/PA3
GPIO8
GPIO9
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA2
Figure 9. Port and Signal Mapping
GPIF Master
→
→
←
←
←
↔
↔
↔
↔
↔
↔
↔
↔
↔
←
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
PA5
PA3/WU2
PA2
PA1/INT1#
PA0/INT0#
RDY0
RDY1
CTL0
CTL1
CTL2
GPIO9
PA7
PA6
PA4
GPIO8
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
from the default NAND firmware image, which actually utilizes
GPIF Master mode. The signals on the left edge of the ‘Port’
column are common to all modes of the NX2LP-Flex. The
8051 selects the interface mode using the IFCONFIG[1:0]
register bits. Port mode is the power-on default configuration.
Figure 10 details the pinout of the 56-pin package and lists pin
names for all modes of operation. Pin names with an asterisk
(*) feature programmable polarity.
↔
↔
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↔
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↔
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↔
→
→
←
←
←
↔
↔
←
↔
←
←
←
↔
↔
←
Slave FIFO
SLRD
SLWR
FLAGA
FLAGB
FLAGC
FIFOADR1
PA3/WU2
SLOE
PA1/INT1#
GPIO9
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
FLAGD/SLCS#/PA7
PKTEND
FIFOADR0
PA0/INT0#
GPIO8
CY7C68033/CY7C68034
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
→
→
←
←
←
←
←
←
←
←
→
↔
↔
↔
←
Default NAND
Firmware Use
R_B1#
R_B2#
WE#
RE0#
RE1#
GPIO1
GPIO0
WP_SW#
WP_NF#
LED2#
LED1#
GPIO9
CE7#/GPIO7
CE6#/GPIO6
CE5#/GPIO5
CE4#/GPIO4
CE3#/GPIO3
CE2#/GPIO2
CE1#
CE0#
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
ALE
CLE
GPIO8
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