CY7C68034-56LFXC Cypress Semiconductor Corp, CY7C68034-56LFXC Datasheet - Page 7

• Manufacturer Part Number: CY7C68034-56LFXC
• Description: IC USB NX2LP NAND CNTRLR 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68034-56LFXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• No. Of I/o's: 12
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Digital Ic Case Style: QFN
• Supply Voltage Range: 3V To 3.6V
• Core Size: 8 Bit
• Program Memory Size: 15KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 001-04247 Rev. *D
Table 4. Individual FIFO/GPIF Interrupt Sources
If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the NX2LP-Flex substitutes its INT4VEC byte.
Therefore, if the high byte (‘page’) of a jump-table address is
preloaded at location 0x554, the automatically-inserted
INT4VEC byte at 0x555 will direct the jump to the correct
address out of the 14 addresses within the page. When the
ISR occurs, the NX2LP-Flex pushes the program counter onto
its stack then jumps to address 0x553, where it expects to find
a ‘jump’ instruction to the ISR Interrupt service routine.
Reset and Wakeup
Reset Pin
The input pin RESET#, will reset the NX2LP-Flex when
asserted. This pin has hysteresis and is active LOW. When a
crystal is used as the clock source for the NX2LP-Flex, the
Note
1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 μs.
RESET#
Priority
V
CC
10
12
13
14
11
1
2
3
4
5
6
7
8
9
INT4VEC Value
T
Power-on Reset
RESET
0x5AC
0x58C
0x59C
0x5A0
0x5A4
0x5A8
0x580
0x588
0x590
0x594
0x598
0x5B0
0x5B4
0x584
Figure 5. Reset Timing Plots
GPIFDONE
GPIFWF
V
3.3V
3.0V
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
EP6EF
EP8EF
EP2FF
EP4FF
EP6FF
EP8FF
0V
IL
RESET#
reset period must allow for the stabilization of the crystal and
the PLL. This reset period should be approximately 5 ms after
V
clock signal, the internal PLL stabilizes in 200 μs after V
reached 3.0V
and a reset applied during operation. A power-on reset is
defined as the time reset is asserted while power is being
applied to the circuit. A powered reset is defined to be when
the NX2LP-Flex has previously been powered on and
operating and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation and can be found
on the Cypress web site. For more information on reset imple-
mentation for the EZ-USB family of products visit the
http://www.cypress.com website.
V
CC
CC
Endpoint 2 Programmable Flag
Endpoint 6 Programmable Flag
Endpoint 2 Empty Flag
Endpoint 4 Empty Flag
Endpoint 6 Empty Flag
Endpoint 8 Empty Flag
Endpoint 4 Full Flag
Endpoint 6 Full Flag
GPIF Waveform
Endpoint 4 Programmable Flag
Endpoint 8 Programmable Flag
Endpoint 2 Full Flag
Endpoint 8 Full Flag
GPIF Operation Complete
has reached 3.0V. If the crystal input pin is driven by a
[1]
. Figure 5 shows a power-on reset condition
T
CY7C68033/CY7C68034
RESET
Powered Reset
Notes
V
3.3V
0V
IL
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CC
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