CY7C68034-56LFXC Cypress Semiconductor Corp, CY7C68034-56LFXC Datasheet - Page 31

• Manufacturer Part Number: CY7C68034-56LFXC
• Description: IC USB NX2LP NAND CNTRLR 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68034-56LFXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• No. Of I/o's: 12
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Digital Ic Case Style: QFN
• Supply Voltage Range: 3V To 3.6V
• Core Size: 8 Bit
• Program Memory Size: 15KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 001-04247 Rev. *D
PCB Layout Recommendations
The following recommendations should be followed to ensure
reliable high-performance operation:
Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
Note
16. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High
• At least a four-layer impedance controlled boards is recom-
• Specify impedance targets (ask your board vendor what
• To control impedance, maintain trace widths and trace
• Minimize any stubs to avoid reflected signals.
• Connections between the USB connector shell and signal
• Bypass/flyback caps on VBUS, near connector, are recom-
• DPLUS and DMINUS trace lengths should be kept to within
• Maintain a solid ground plane under the DPLUS and
• No vias should be placed on the DPLUS or DMINUS trace
• Isolate the DPLUS and DMINUS traces from all other signal
mended to maintain signal quality.
they can achieve) to meet USB specifications.
spacing.
ground must be done near the USB connector.
mended.
2 mm of each other in length, with preferred length of
20–30 mm.
DMINUS traces. Do not allow the plane to be split under
these traces.
routing unless absolutely necessary.
traces as much as possible.
Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
Via hole for thermally connecting the
QFN to the circuit board ground plane.
Figure 21. Cross-section of the Area Underneath the QFN Package.
PCB Material
[16]
Cu Fill
Solder Mask
0.013” dia
0.017” dia
heat transfer area below the package to provide a good
thermal bond to the circuit board. A Copper (Cu) fill is to be
designed into the PCB as a thermal pad under the package.
Heat is transferred from the NX2LP-Flex to the PCB through
the device’s metal paddle on the bottom side of the package.
It is then conducted from the PCB’s thermal pad to the inner
ground plane by a 5 x 5 array of vias. A via is a plated through
hole in the PCB with a finished diameter of 13 mil. The QFN’s
metal die paddle must be soldered to the PCB’s thermal pad.
Solder mask is placed on the board top side over each via to
resist solder flow into the via. The mask on the top side also
minimizes outgassing during the solder reflow process.
For further information on this package design please refer to
the application note Surface Mount Assembly of AMKOR’s
MicroLeadFrame (MLF) Technology. This application note can
be downloaded from AMKOR’s website from the following
URL:
http://www.amkor.com/products/notes_papers/
MLF_AppNote_0902.pdf
The application note provides detailed information on board
mounting guidelines, soldering flow, rework process, etc.
Figure 21 below displays a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50%
solder coverage. The thickness of the solder paste template
should be 5 mil. It is recommended that ‘No Clean’ type 3
solder paste is used for mounting the part. Nitrogen purge is
recommended during reflow.
Figure 22 is a plot of the solder mask pattern and Figure 23
displays an X-Ray image of the assembly (darker areas
indicate solder)
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and the Ground Plane.
Cu Fill
PCB Material
CY7C68033/CY7C68034
.
Page 31 of 33