CY7C68034-56LFXC Cypress Semiconductor Corp, CY7C68034-56LFXC Datasheet - Page 15

• Manufacturer Part Number: CY7C68034-56LFXC
• Description: IC USB NX2LP NAND CNTRLR 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68034-56LFXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• No. Of I/o's: 12
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Digital Ic Case Style: QFN
• Supply Voltage Range: 3V To 3.6V
• Core Size: 8 Bit
• Program Memory Size: 15KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 001-04247 Rev. *D
Table 8. NX2LP-Flex Pin Descriptions (continued)
Port A
Number
56 QFN
Pin
13
14
15
16
44
33
34
35
36
37
38
Default Pin
GPIO8
Reserved#
SCL
SDATA
WAKEUP
PA0 or
INT0#
PA1 or
INT1#
PA2 or
SLOE
PA3 or
WU2
PA4 or
FIFOADR0
PA5 or
FIFOADR1
Name
Firmware
WP_SW#
WP_NF#
Unused
Usage
GPIO8
LED1#
LED2#
NAND
CLE
ALE
N/A
N/A
N/A
Type
Input
I/O/Z
Input
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Pin
OD
OD
Default
(PA0)
(PA1)
(PA2)
(PA3)
(PA4)
(PA5)
State
[6]
N/A
N/A
Z
Z
I
I
I
I
I
I
I
GPIO8: is a bidirectional IO port pin.
Reserved. Connect to ground.
Clock for the I
even if no I
Data for the I
if no I
USB Wakeup. If the 8051 is in suspend, asserting this pin starts up
the oscillator and interrupts the 8051 to allow it to exit the suspend
mode. Holding WAKEUP asserted inhibits the EZ-USB chip from
suspending. This pin has programmable polarity, controlled by
WAKEUP[4].
Multiplexed pin whose function is selected by PORTACFG[0]
PA0 is a bidirectional IO port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is
either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
CLE is the NAND Command Latch Enable signal.
Multiplexed pin whose function is selected by PORTACFG[1]
PA1 is a bidirectional IO port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is
either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
ALE is the NAND Address Latch Enable signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPINPOLAR[4]) for the slave FIFOs connected to FD[7:0] or
FD[15:0].
LED1# is the data activity indicator LED sink pin.
Multiplexed pin whose function is selected by WAKEUP[7] and
OEA[3]
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN
bit (WAKEUP[1]) and polarity set by WU2POL (WAKEUP[4]). If the
8051 is in suspend and WU2EN = 1, a transition on this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the suspend
mode. Asserting this pin inhibits the chip from suspending, if
WU2EN = 1.
LED2# is the chip activity indicator LED sink pin.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs
connected to FD[7:0] or FD[15:0].
WP_NF# is the NAND write-protect control output signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs
connected to FD[7:0] or FD[15:0].
WP_SW# is the NAND write-protect switch input signal.
2
C peripheral is attached.
2
C peripheral is attached.
2
C interface. Connect to VCC with a 2.2K resistor, even
2
C interface. Connect to VCC with a 2.2K resistor,
CY7C68033/CY7C68034
Description
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