CY7C68034-56LFXC Cypress Semiconductor Corp, CY7C68034-56LFXC Datasheet

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... Master or slave operation — Uses external clock or asynchronous strobes — Easy interface to ASIC and DSP ICs • Available in space saving, 56-pin QFN package CY7C68034 Only Silicon Features: • Ideal for battery powered applications — Suspend current: 100 μA (typ.) CY7C68033 Only Silicon Features: • ...

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... NAND Overview Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB NX2LP-Flex (CY7C68033/CY7C68034 firmware-based, programmable (CY7C68023/CY7C68024), low-power USB 2.0 NAND Flash controller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral ...

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... I C Bus NX2LP supports the I SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to 3.3V, even device is connected. The I only available for use after the initial NAND access. CY7C68033/CY7C68034 Figure 3. Crystal Configuration. 24 MHz × PLL 2 C bus as a master only at 100-/400-kHz ...

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... If no NAND Flash is detected valid firmware is found, the NX2LP-Flex uses the default values from internal ROM space for manufacturing mode operation. The two modes of operation are described in the section ”Normal Operation Mode” on page 5 and ”Manufacturing Mode” on page 5. CY7C68033/CY7C68034 SCON1 ...

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... EZ-USB microcontrollers. This is due to the additional NAND boot logic that is present in the NX2LP-Flex ROM space. Also, these values are fixed and cannot be changed in the firmware. CY7C68033/CY7C68034 Default VID/PID/DID 0x04B4 Cypress Semiconductor ® 0x8613 EZ-USB ...

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... Just as the USB Interrupt is shared among 27 individual USB-interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources. CY7C68033/CY7C68034 Notes Page ...

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... NX2LP-Flex, the RESET RESET Power-on Reset Note 1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 μs. Document #: 001-04247 Rev. *D Source EP2PF Endpoint 2 Programmable Flag EP4PF Endpoint 4 Programmable Flag EP6PF ...

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... E780 E77F E740 E73F E700 E6FF E500 E4FF E480 E47F E400 E3FF E200 E1FF E000 CY7C68033/CY7C68034 FFFF 7.5 kBytes USB registers and 4 kBytes FIFO buffers (RD#, WR#) E200 E1FF 512 Bytes RAM Data (RD#, WR#)* E000 3FFF 15 kBytes RAM Code and Data (PSEN#, RD#, ...

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... EP8 EP8 512 512 512 1024 1024 512 512 512 [ bulk 64 int 64 bulk 64 int 64 bulk out (2×) 64 int out (2×) CY7C68033/CY7C68034 double buffered; EP6–512 quad EP2 EP2 EP2 EP2 EP2 512 1024 1024 1024 512 1024 ...

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... GPIF functionality to interface internally controls with NAND Flash. The GPIF on the NX2LP-Flex features three programmable control outputs (CTL) and two general-purpose ready inputs (RDY). The GPIF data bus width can bits. Because CY7C68033/CY7C68034 64 bulk out (2×) 64 iso in (2×) 64 bulk in (2× ...

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... I C Interface General-Purpose Access The 8051 can control peripherals connected to the I 2 using the I CTL and I master control only and is never an I CY7C68033/CY7C68034 2 C port that the 8051, once running uses devices. The I C port operates in master 2 C post is disabled at startup and only ...

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... INT1#/PA1 PA1/INT1# ↔ ↔ PA0/INT0# PA0/INT0# ↔ ↔ GPIO8 GPIO8 GPIO8 ← ← GPIO9 GPIO9 GPIO9 CY7C68033/CY7C68034 Default NAND Firmware Use ↔ CE7#/GPIO7 ↔ CE6#/GPIO6 ↔ CE5#/GPIO5 ↔ ↔ CE4#/GPIO4 CE3#/GPIO3 ↔ CE2#/GPIO2 ↔ ...

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... Figure 10. CY7C68033/CY7C68034 56-pin QFN Pin Assignment RDY0/*SLRD 1 RDY1/*SLWR 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 AVCC 7 DPLUS 8 DMINUS 9 AGND 10 VCC 11 GND 12 GPIO8 13 RESERVED# 14 Document #: 001-04247 Rev. *D CY7C68033/CY7C68034 56-pin QFN CY7C68033/CY7C68034 RESET# 42 GND 41 PA7/*FLAGD/SLCS# 40 PA6/*PKTEND 39 PA5/FIFOADR1 38 PA4/FIFOADR0 37 PA3/*WU2 36 PA2/*SLOE ...

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... RE0 NAND read enable output signal. O/Z H Multiplexed pin whose function is selected by IFCONFIG[1:0]. CTL2 is a GPIF control output. FLAGC is a programmable slave-FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins. RE1 NAND read enable output signal. CY7C68033/CY7C68034 Description Page ...

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... WP_NF# is the NAND write-protect control output signal. I/O/Z I Multiplexed pin whose function is selected by IFCONFIG[1:0]. (PA5) PA5 is a bidirectional I/O port pin. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. WP_SW# is the NAND write-protect switch input signal. CY7C68033/CY7C68034 Description Page ...

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... FD[7] is the bidirectional FIFO/GPIF data bus. DD7 is a bidirectional NAND data bus signal. I/O/Z I Multiplexed pin whose function is selected by the IFCONFIG[1:0] (PD0) and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. CE0 NAND chip enable output signal. CY7C68033/CY7C68034 Description Page ...

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... GPIO7 is a general purpose I/O signal. Power N/A Analog V . Connect this pin to 3.3V power source. This signal CC provides power to the analog section of the chip. Ground N/A Analog Ground. Connect to ground with as short a path as possible. Power N Connect to 3.3V power source. CC Ground N/A Ground. CY7C68033/CY7C68034 Description Page ...

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... PL7 PL6 PL5 PL4 PL3 PL7 PL6 PL5 PL4 PL3 PL7 PL6 PL5 PL4 PL3 CY7C68033/CY7C68034 Default Access xxxxxxxx RW reserved reserved reserved 00000000 R CLKINV CLKOE 8051RES 00000010 rrbbbbbr GSTATE IFCFG1 IFCFG0 10000000 RW FLAGA2 FLAGA1 FLAGA0 00000000 RW FLAGC2 FLAGC1 FLAGC0 00000000 RW EP2 ...

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... EDGEPF EDGEPF EP8 EP6 EP4 0 0 EP8 EP6 EP4 EP8 EP6 EP4 EP2 EP1 CY7C68033/CY7C68034 Default Access 00000000 W LINE10 LINE9 LINE8 00000000 R LINE2 LINE1 LINE0 00000000 R COL0 LINE17 LINE16 00000000 R LINE10 LINE9 LINE8 00000000 R LINE2 LINE1 LINE0 00000000 R COL0 0 0 00000000 R ...

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... BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 BC6 BC5 BC4 BC3 CY7C68033/CY7C68034 Default Access EP0 0 IBN xxxxxx0x bbbbbbrb SUTOK SOF SUDAV 00000000 RW SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb EP1IN EP0OUT EP0IN 00000000 RW EP1IN EP0OUT EP0IN GPIFWF GPIFDONE 00000000 RW ...

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... CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 CTL0E3 CTL0E2 CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE 0 SLAVE RDYASYNC CTLTOGL SUSTAIN CY7C68033/CY7C68034 Default Access 0 BUSY STALL 10000000 bbbbbbrb 0 BUSY STALL 00000000 bbbbbbrb 0 BUSY STALL 00000000 bbbbbbrb EMPTY 0 STALL 00101000 rrrrrrrb EMPTY 0 ...

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... DISCON CY7C68033/CY7C68034 Default Access 00000010 RW TC26 TC25 TC24 00000000 RW TC18 TC17 TC16 00000000 RW TC10 TC9 TC8 00000000 RW TC2 TC1 TC0 00000001 RW 00000000 RW 0 FS1 FS0 00000000 FIFO2FLAG 00000000 xxxxxxxx W 0 FS1 FS0 00000000 FIFO4FLAG 00000000 xxxxxxxx W 0 FS1 FS0 00000000 FIFO6FLAG 00000000 RW ...

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... PS1 PT2 PS0 PT1 DONE D15 D14 D13 D12 D11 CY7C68033/CY7C68034 Default Access A10 A9 A8 00000000 00000000 RW A10 A9 A8 00000000 SEL 00000000 IDLE 00110000 RW IT1 IE0 IT0 00000000 00000000 00000000 00000000 RW D10 D9 D8 00000000 RW D10 D9 D8 00000000 RW MD2 MD1 MD0 00000001 RW ...

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... Max Output Current, per I/O port................................. 10 mA Operating Conditions T (Ambient Temperature Under Bias) ............. 0°C to +70°C A [11] Supply Voltage............................................+3.00V to +3.60V Ground Voltage.................................................................. (Oscillator or Crystal Frequency).... 24 MHz ± 100 ppm OSC (Parallel Resonant) CY7C68033/CY7C68034 Default Access xxxxxxxx R RB8_1 TI_1 RI_1 00000000 RW ...

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... RESET Pin Reset After powered on USB Transceiver USB 2.0-compliant in full- and high-speed modes. AC Electrical Characteristics USB Transceiver USB 2.0-compliant in full- and high-speed modes. Note 12. Measured at Max V , 25°C. CC Document #: 001-04247 Rev. *D CY7C68033/CY7C68034 Conditions 0< V < OUT I = –4 mA OUT Except D+/D– ...

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... IFCLK. x 15. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document #: 001-04247 Rev RDpwh t RDpwl t XFLG t XFD N N OEon OEoff [15] Description t WRpwh t WRpwl t t FDH SFD t XFD Description CY7C68033/CY7C68034 [13] Min. Max. Unit 10.5 ns 10.5 ns [13] [15] Min. Max. Unit ...

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... FIFOADR[1:0] to FLAGS Output Propagation Delay XFLG t FIFOADR[1:0] to FIFODATA Output Propagation Delay XFD Document #: 001-04247 Rev PEpwh t PEpwl t XFLG [15] Description t OEoff t OEon Description t XFLG t XFD N N+1 Description CY7C68033/CY7C68034 [9] Min. Max. Unit 115 ns [13] Min. Max. Unit 10.5 ns 10.5 ns [13] Min. Max. Unit 10.7 ns 14.3 ...

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... SFA t t T=0 RDpwl RDpwh T=2 T=3 T=4 t XFLG t XFD N N+1 t OEon OEoff T=1 SLRD SLOE SLOE N N+1 N+1 N Not Driven N CY7C68033/CY7C68034 [13] t FAH Min. Max [13] t FAH RDpwl RDpwh RDpwl RDpwh T=5 T=6 t XFLG t XFD t XFD N+3 N+2 t OEoff T=7 ...

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... SFD signal at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum de-asserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. CY7C68033/CY7C68034 from the activating edge of SLRD. In XFD [13] t FAH ...

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... Ordering Information Table 17.Ordering Information Ordering Code Silicon for battery-powered applications CY7C68034-56LFXC Silicon for non-battery-powered applications CY7C68033-56LFXC Development Kit CY3686 Package Diagram Figure 20. 56-Lead QFN LF56A DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-220 TOP VIEW 7.90[0.311] A 8.10[0.319] 7.70[0.303] 7.80[0.307 0.80[0.031] DIA. ...

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... X-Ray image of the assembly (darker areas indicate solder) 0.017” dia Solder Mask Cu Fill Cu Fill 0.013” dia PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane. CY7C68033/CY7C68034 . Page ...

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... Cypress against all charges. Figure 22. Plot of the Solder Mask (White Area) Figure 23. X-ray Image of the Assembly 2 C system, provided that the system conforms to the I CY7C68033/CY7C68034 2 C Standard Specification Page ...

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... Document History Page Document Title: CY7C68033/CY7C68034 EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller Document #: 001-04247 Rev. *D REV. ECN NO. Issue Date ** 388499 See ECN *A 394699 See ECN *B 400518 See ECN *C 433952 See ECN *D 498295 See ECN Document #: 001-04247 Rev. *D Orig. of Change ...